CN-115332350-B - LDMOS device and preparation method thereof

Abstract

The application belongs to the technical field of semiconductors, and provides an LDMOS device and a preparation method thereof, wherein the LDMOS device comprises: the LDMOS device comprises a semiconductor substrate, a buried oxide region, a P-type well region, a source region, a P-type base region, a drain region, a drift region, a gate oxide layer, a gate region, a source electrode, a drain electrode, a gate electrode and a gate extension region. By arranging the grid expansion region between the grid region and the drain electrode, a high-concentration electron channel with low resistance from the drain region to the source region can be formed above the drift region, so that the on-resistance of the LDMOS device is reduced, and the semiconductor substrate and the drift region are arranged in a staggered manner, so that breakdown of the device due to an electric field peak formed in the semiconductor substrate is avoided, the on-resistance of the LDMOS device is reduced while the breakdown voltage of the LDMOS device is improved, and the problem that the existing LDMOS device cannot be balanced in terms of the breakdown voltage and the on-resistance is solved.

Inventors

• CHEN TAO
• HUANG HUIQIN

Assignees

• 天狼芯半导体(成都)有限公司

Dates

Publication Date

20260505

Application Date

20220826

Claims (10)

1. 1. An LDMOS device, characterized in that the LDMOS device comprises: The oxygen-buried region is of an L-shaped structure; a semiconductor substrate arranged on the back surface of the buried oxide region; the P-type well region is arranged on the horizontal part of the buried oxide region, wherein the P-type well region is of an L-shaped structure; the source region is arranged on the horizontal part of the P-type well region; The P-type base region is arranged on the horizontal part of the buried oxide region and is respectively contacted with the P-type well region and the source region; a drain region arranged on the vertical part of the buried oxide region; The drift region is arranged on the vertical part of the buried oxide region and is positioned between the P-type well region and the drain region; the grid electrode oxide layer is arranged on the source electrode region, the P-type well region, the drain electrode region and the drift region, wherein the grid electrode oxide layer is of an L-shaped structure; A gate region on a horizontal portion of the gate oxide layer; a source electrode in contact with the source region; A drain electrode in contact with the drain region; A gate electrode in contact with the gate region; the gate extension region is arranged between the gate region and the drain electrode and is positioned on the gate oxide layer; Wherein the semiconductor substrate and the projection of the drift region on the buried oxide region do not overlap.
2. 2. The LDMOS device of claim 1, wherein the gate extension region comprises: The first P-type doped region is arranged on the horizontal part of the gate oxide layer and is in contact with the gate region; the second P-type doped region is arranged on the horizontal part of the grid electrode oxide layer and is in contact with the first P-type doped region; the first N-type doped region is arranged on the horizontal part of the grid electrode oxide layer and is in contact with the second P-type doped region; and the third P-type doped region is arranged on the horizontal part of the grid electrode oxide layer and is contacted with the first N-type doped region.
3. 3. The LDMOS device of claim 1, wherein a thickness of the drift region is less than a thickness of a vertical portion of the P-type well region.
4. 4. The LDMOS device of claim 3, wherein the drift region has a thickness of 0.08 μm to 0.12 μm.
5. 5. The LDMOS device of claim 3, wherein a width of the drift region is less than a width of the gate extension region.
6. 6. The LDMOS device of claim 1, wherein the width of the semiconductor substrate is the sum of the widths of the vertical portions of the P-type base region, the source region, and the P-type well region.
7. 7. The LDMOS device of claim 1, wherein a sum of a width of a horizontal portion of the buried oxide region and a width of a vertical portion of the buried oxide region is equal to a sum of a width of the semiconductor substrate, a width of the drift region, and a width of the drain region.
8. 8. The LDMOS device of claim 1, wherein a thickness of the P-type base region is greater than a thickness of the source region.
9. 9. The LDMOS device of claim 1, wherein a thickness of the drift region is equal to a thickness of the drain region.
10. 10. The preparation method of the LDMOS device is characterized by comprising the following steps of: forming an oxygen-buried region on a semiconductor substrate, wherein the back surface of the oxygen-buried region is in contact with the semiconductor substrate, and the oxygen-buried region is in an L-shaped structure; Forming a P-type well region and a P-type base region on the horizontal part of the buried oxide region, wherein the P-type well region is of an L-shaped structure, and the P-type base region and the P-type well region are adjacently arranged; forming a source region on the horizontal part of the P-type well region, wherein the source region is contacted with the P-type base region; Forming a drift region and a drain region on a vertical portion of the buried oxide region, wherein the drift region and the drain region are adjacently arranged; Forming a grid oxide layer on the source region, the P-type well region, the drain region and the drift region, wherein the grid oxide layer is of an L-shaped structure; forming a gate region and a gate extension region on a horizontal portion of the gate oxide layer, wherein the gate region is in contact with a vertical portion of the gate oxide layer; forming a source electrode on the source region, forming a drain electrode on the drain region and forming a gate electrode on the gate region, wherein the gate extension is located between the gate region and the drain electrode; and selectively etching the semiconductor substrate so that the projections of the semiconductor substrate and the drift region on the buried oxide region do not overlap.

Description

LDMOS device and preparation method thereof Technical Field The application belongs to the technical field of semiconductors, and particularly relates to an LDMOS device and a preparation method thereof. Background With the improvement of integrated circuit integration level, a Lateral Diffusion Metal Oxide Semiconductor (LDMOS) is often applied to the design of a high-voltage power integrated circuit due to the outstanding advantages of high voltage resistance, large driving current, large output power, good switching characteristics and the like, and is particularly commonly applied to the occasion of high-voltage power amplification, and one important parameter of the LDMOS is the on-resistance of the LDMOS. In practical applications, on-resistance is an important parameter closely related to performance, and its magnitude is closely related to the maximum output power of the LDMOS. For high performance power devices, in addition to a high breakdown voltage, as low an on-resistance as possible is required. The on-resistance always decreases with increasing doping concentration of the drift region, whereas the breakdown voltage is typically more complex with increasing doping concentration of the drift region. Therefore, we should optimize the relationship between the breakdown voltage and the on-resistance, and reduce the on-resistance as much as possible under the condition of ensuring a certain breakdown voltage, so as to obtain the output power as much as possible. Some documents study the on-resistance of the traditional doped LDMOS and have achieved many results, but the contradiction between the on-resistance and the breakdown voltage is not solved at all. The need for high performance devices has focused the research on LDMOS on achieving both high breakdown voltage and low on-resistance. Therefore, the existing LDMOS device cannot balance the breakdown voltage and the on-resistance. Disclosure of Invention In order to solve the technical problems, the embodiment of the application provides an LDMOS device and a preparation method thereof, which can solve the problem that the existing LDMOS device cannot be balanced in terms of breakdown voltage and on-resistance. The embodiment of the application provides an LDMOS device, which comprises: The oxygen-buried region is of an L-shaped structure; a semiconductor substrate arranged on the back surface of the buried oxide region; the P-type well region is arranged on the horizontal part of the buried oxide region, wherein the P-type well region is of an L-shaped structure; the source region is arranged on the horizontal part of the P-type well region; The P-type base region is arranged on the horizontal part of the buried oxide region and is respectively contacted with the P-type well region and the source region; a drain region arranged on the vertical part of the buried oxide region; The drift region is arranged on the vertical part of the buried oxide region and is positioned between the P-type well region and the drain region; the grid electrode oxide layer is arranged on the source region, the P-type well region and the drift region, wherein the grid electrode oxide layer is of an L-shaped structure; A gate region on a horizontal portion of the gate oxide layer; a source electrode in contact with the source region; A drain electrode in contact with the drain region; A gate electrode in contact with the gate region; the gate extension region is arranged between the gate region and the drain electrode and is positioned on the gate oxide layer; The semiconductor substrate and the drift region are arranged in a staggered mode. In one embodiment, the gate extension region includes: The first P-type doped region is arranged on the horizontal part of the gate oxide layer and is in contact with the gate region; the second P-type doped region is arranged on the horizontal part of the grid electrode oxide layer and is in contact with the first P-type doped region; the first N-type doped region is arranged on the horizontal part of the grid electrode oxide layer and is in contact with the second P-type doped region; and the third P-type doped region is arranged on the horizontal part of the grid electrode oxide layer and is contacted with the first N-type doped region. In one embodiment, the thickness of the drift region is less than the thickness of the vertical portion of the P-type well region. In one embodiment, the drift region has a thickness of 0.08 μm to 0.12 μm. In one embodiment, the width of the drift region is less than the width of the gate extension region. In one embodiment, the width of the semiconductor substrate is the sum of the widths of the vertical portions of the P-type base region, the source region, and the P-type well region. In one embodiment, a sum of a width of the horizontal portion of the buried oxide region and a width of the vertical portion of the buried oxide region is equal to a sum of a width of the semiconductor substrate