CN-115360143-B - Gate structure in semiconductor device and method of forming the same

Abstract

The present disclosure relates to gate structures in semiconductor devices and methods of forming the same. A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are located in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer including a first portion over the first gate dielectric layer and a second portion over the second gate dielectric layer, removing the second portion of the fluorine-containing layer, performing an annealing process to diffuse fluorine in the first portion of the fluorine-containing layer into the first gate dielectric layer, and forming a first work function layer and a second work function layer over the first gate dielectric layer and the second gate dielectric layer, respectively, after the annealing process.

Inventors

• LI XINYI
• WU JUNYI
• ZHANG WEN
• Zhang Xiangbi
• Zhao Huanglin
• CHENG ZHONGLIANG
• XU ZHIAN
• LI KUNYU
• SHEN ZEMIN
• Dong Yandian

Assignees

• 台湾积体电路制造股份有限公司
• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260421

Application Date

20220402

Priority Date

20220221

Claims (20)

1. 1. A method, comprising: Removing the first and second dummy gate stacks to form first and second trenches, wherein the first and second dummy gate stacks are located in first and second device regions, respectively; Depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively; forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer and a second portion over the second gate dielectric layer; removing a second portion of the fluorine-containing layer; performing an annealing process to diffuse fluorine in the first portion of the fluorine-containing layer into the first gate dielectric layer, and Forming a first work function layer and a second work function layer over the first gate dielectric layer and the second gate dielectric layer, respectively, Wherein the method further comprises diffusing a dipole dopant species into the first gate dielectric layer after performing the annealing process and forming a combined fluorine-dipole species in the first gate dielectric layer.
2. 2. The method of claim 1, wherein forming the fluorine-containing layer comprises depositing the fluorine-containing layer using a fluorine-containing precursor.
3. 3. The method of claim 2, wherein the fluorine-containing precursor comprises WF 6 .
4. 4. The method of claim 3, wherein depositing the fluorine-containing layer is performed using an additional chemistry comprising silane.
5. 5. The method of claim 1, wherein forming the fluorine-containing layer comprises immersing a corresponding wafer comprising the first gate dielectric layer and the second gate dielectric layer in a fluorine-containing process gas.
6. 6. The method of claim 5, wherein the soaking results in a surface portion of the first gate dielectric layer in contact with the fluorine-containing process gas having an increased atomic percentage of fluorine and results in the surface portion forming the fluorine-containing layer.
7. 7. The method of claim 5, wherein the fluorine-containing process gas is selected from NF 3 、WF 6 or a combination thereof.
8. 8. The method of claim 1, further comprising: A protective layer comprising a first portion and a second portion is deposited on the first gate dielectric layer and the second gate dielectric layer, respectively, prior to forming the fluorine-containing layer.
9. 9. The method of claim 8, wherein in the step of removing the second portion of the fluorine-containing layer, a portion of the protective layer is also removed from over the second gate dielectric layer.
10. 10. The method of claim 9, further comprising, after the annealing process, removing an additional portion of the protective layer from over the first gate dielectric layer.
11. 11. The method of claim 1, further comprising forming a first source/drain region on a side of the first work function layer and a second source/drain region on a side of the second work function layer, wherein the first source/drain region and the second source/drain region are of opposite conductivity types.
12. 12. The method of claim 1, further comprising forming a first source/drain region on a side of the first work function layer and a second source/drain region on a side of the second work function layer, wherein the first source/drain region and the second source/drain region are the same conductivity type.
13. 13. The method of claim 1, wherein the first dummy gate stack is formed on a top surface and sidewalls of a multi-layer stack, and wherein the multi-layer stack comprises a plurality of sacrificial layers and a plurality of nanostructures arranged alternately.
14. 14. A method, comprising: forming a first dummy gate stack on a top surface and sidewalls of a first multi-layer stack, wherein the first multi-layer stack includes a first plurality of sacrificial layers and a first plurality of nanostructures arranged alternately; Forming a second dummy gate stack on a top surface and sidewalls of a second multi-layer stack, wherein the second multi-layer stack includes a second plurality of sacrificial layers and a second plurality of nanostructures arranged alternately; removing the first dummy gate stack and the second dummy gate stack to form a first recess and a second recess, respectively, in a dielectric layer; removing the first plurality of sacrificial layers and the second plurality of sacrificial layers; depositing a first gate dielectric surrounding the first plurality of nanostructures; Depositing a second gate dielectric surrounding the second plurality of nanostructures; depositing a first protective layer and a second protective layer on the first gate dielectric and the second gate dielectric, respectively; forming a first fluorine-containing layer and a second fluorine-containing layer on the first protective layer and the second protective layer, respectively; Removing the second fluorine-containing layer; after removing the second fluorine-containing layer, performing an annealing process, wherein the first fluorine-containing layer is subjected to the annealing process, and After the annealing process, removing the first fluorine-containing layer, Wherein the method further comprises diffusing a dipole dopant species into the first gate dielectric after performing the annealing process and forming a combined fluorine-dipole species in the first gate dielectric.
15. 15. The method of claim 14, further comprising: removing the first protective layer and the second protective layer, and And forming a work function layer in a space left by the removed first protective layer and the removed second protective layer.
16. 16. The method of claim 14, further comprising forming a first work function layer and a second work function layer on the first protective layer and the second gate dielectric layer, respectively.
17. 17. The method of claim 14, wherein forming the first and second fluorine-containing layers comprises a deposition process or a soak process.
18. 18. A method, comprising: forming a first nanostructure in a first trench, wherein a first gate spacer comprises portions on opposite sides of the first trench; forming a second nanostructure in a second trench, wherein a second gate spacer comprises portions on opposite sides of the second trench; Depositing a first gate dielectric extending into the first trench to surround the first nanostructure; depositing a second gate dielectric extending into the second trench to surround the second nanostructure, and Adding fluorine in the first gate dielectric after forming the first gate dielectric and the second gate dielectric, wherein fluorine in the second gate dielectric remains substantially unchanged when fluorine is added to the first gate dielectric, Wherein the method further comprises diffusing a dipole dopant species into the first gate dielectric after fluorine is added to the first gate dielectric and forming a combined fluorine-dipole species in the first gate dielectric.
19. 19. The method of claim 18, wherein the adding fluorine comprises: forming a fluorine-containing layer on the first gate dielectric, and An annealing process is performed to drive fluorine in the fluorine-containing layer into the first gate dielectric.
20. 20. The method of claim 19 wherein the fluorine-containing layer is further formed to extend over the second gate dielectric and the method further comprises, prior to the annealing process, removing the fluorine-containing layer from the second trench.

Description

Gate structure in semiconductor device and method of forming the same Technical Field The present disclosure relates to the field of semiconductors, and more particularly, to gate structures in semiconductor devices and methods of forming the same. Background Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing layers of insulating or dielectric, conductive, and semiconductor materials over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon. The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given chip area. However, as the minimum feature size decreases, additional problems arise and should be addressed. Disclosure of Invention A first aspect of the present disclosure relates to a method comprising removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench, wherein the first dummy gate stack and the second dummy gate stack are located in a first device region and a second device region, respectively, depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer and a second portion over the second gate dielectric layer, removing the second portion of the fluorine-containing layer, performing an annealing process to diffuse fluorine in the first portion of the fluorine-containing layer into the first gate dielectric layer, and forming a first work function layer and a second work function layer over the first gate dielectric layer and the second gate dielectric layer, respectively, after the annealing process. A second aspect of the present disclosure relates to a method comprising forming a first dummy gate stack on a top surface and sidewalls of a first multi-layer stack, wherein the first multi-layer stack comprises a first plurality of sacrificial layers and a first plurality of nanostructures disposed alternately, forming a second dummy gate stack on a top surface and sidewalls of a second multi-layer stack, wherein the second multi-layer stack comprises a second plurality of sacrificial layers and a second plurality of nanostructures disposed alternately, removing the first dummy gate stack and the second dummy gate stack to form first recesses and second recesses, respectively, in a dielectric layer, removing the first plurality of sacrificial layers and the second plurality of sacrificial layers, depositing a first gate dielectric surrounding the first plurality of nanostructures, depositing a second gate dielectric surrounding the second plurality of nanostructures, depositing a first protective layer and a second protective layer, respectively, on the first protective layer and the second protective layer, respectively, forming a first fluorine-containing layer and the second fluorine-containing layer, removing the first fluorine-containing layer, and the second fluorine-containing layer, and annealing the first fluorine-containing layer, and the second fluorine-containing layer, after the annealing process, is performed. A third aspect of the present disclosure relates to a method comprising forming a first nanostructure in a first trench, wherein a first gate spacer comprises portions on opposite sides of the first trench, forming a second nanostructure in a second trench, wherein a second gate spacer comprises portions on opposite sides of the second trench, depositing a first gate dielectric extending into the first trench to surround the first nanostructure, depositing a second gate dielectric extending into the second trench to surround the second nanostructure, and adding fluorine in the first gate dielectric after forming the first gate dielectric and the second gate dielectric, wherein fluorine in the second gate dielectric remains substantially unchanged when fluorine is added to the first gate dielectric. Drawings Various aspects of the disclosure may be best understood from the following detailed description when read with the accompanying drawing figures. It is noted that the various features are not drawn to scale in accordance with industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1-4、5A、5B、6A、6B、7A、7B、8A、8B、9A、9B、10A、10B、10C、11A、11B、12A、12B、12C、13A、13B、14-15、16A、16B、17、18、19A、19B、20A、20B、21A、21B、22A、22B、23A、23B、24A、24B、24C、24D and 24E illustrate intermediate stages of forming a Gate