CN-115393163-B - Pipeline Tile address conflict processing circuit and method of graphics processor

CN115393163BCN 115393163 BCN115393163 BCN 115393163BCN-115393163-B

Abstract

The invention relates to a pipeline Tile address conflict processing circuit and method of a graphics processor. The circuit comprises a Tile input data FIFO buffer circuit, a Tile writing judging circuit, a Tile information buffer circuit, a Tile output selecting circuit and a Tile address conflict detecting circuit, wherein the Tile input data FIFO buffer circuit is respectively connected with the Tile writing judging circuit and the Tile information buffer circuit, the Tile writing judging circuit is connected with the Tile information buffer circuit, the Tile information buffer circuit is connected with the Tile address conflict detecting circuit through the Tile output selecting circuit, and the Tile address conflict detecting circuit is connected with the Tile information buffer circuit. The invention adopts the FIFO input interface, has clear interface and time sequence, is easy to integrate, and greatly improves the graphic processing performance of the drawing scene when the conflict address and the non-conflict address exist simultaneously.

Inventors

ZHANG SHU
XU HONGJIE
ZHENG XINJIAN
LI PAN
DU QINQIN

Assignees

西安翔腾微电子科技有限公司
西安翔腾微电子科技有限公司

Dates

Publication Date: 20260421
Application Date: 20220820
Priority Date: 20220820

Claims (7)

1. The circuit comprises a Tile input data FIFO buffer circuit, a Tile write judgment circuit, a Tile information buffer circuit, a Tile output selection circuit and a Tile address conflict detection circuit, wherein the Tile input data FIFO buffer circuit is respectively connected with the Tile write judgment circuit and the Tile information buffer circuit, the Tile write judgment circuit is connected with the Tile information buffer circuit, the Tile information buffer circuit is connected with the Tile address conflict detection circuit through the Tile output selection circuit, the Tile output selection circuit is connected with the Tile information buffer circuit, and the data in a data buffer queue is selected and output according to a mode of grouping and searching priority conflict addresses, namely, the data in the data buffer queue is selected from the maximum position, each time is reduced by 1, and the maximum value is obtained again until the data is reduced to 0; if there is a matching address writing in this process, the address is directly set as the position where the matching address is located, one of the two is selected according to the priority marking bit to output the selected position, the queue is divided into 8 groups according to the sequence from 0 to 31 when the maximum value is selected, each group comprises four queues, one of the four queues is valid and is regarded as being valid, the maximum value is 31 when the eighth group is valid, the maximum value is 27..the third is analogically, the maximum value of the effective value of the zeroth group is 3, the Tile address conflict detection circuit realizes the monitoring of the pixel addresses of all pipeline data processing paths, if the current input Tile is the same as the monitoring Tile coordinate, the feedback conflict signal is used for reserving the data in the cache, otherwise, the information cache queue is cleared, in the Tile address conflict detection circuit, the method comprises the steps of comparing an input Tile address with a Tile address to be monitored in a pipeline, dividing a comparison circuit into four parts for circuit time sequence consideration, namely pipeline 1 address comparison, pipeline 2 address comparison, pipeline 3 address comparison and pipeline 4 address comparison, outputting each part by adopting a trigger, and finally merging and outputting the results of the four parts, wherein a clock period is used by a Tile address conflict detection circuit, a conflict signal is provided for a conflict cache unit at the previous stage and is used as a switching signal for outputting data by the unit, and when the conflict signal is effective, outputting data is invalid and the data is discarded.
2. The pipeline Tile address conflict processing circuit of claim 1, wherein the Tile information buffer circuit comprises a register and a RAM, the Tile write judgment circuit is connected with the register, the register is connected with the RAM, the RAM is connected with the Tile output selection circuit, the Tile input data FIFO buffer circuit is connected with the RAM, and the Tile address conflict detection circuit is connected with the register.
3. The pipeline Tile address conflict processing circuit of claim 2, wherein the Tile input data FIFO buffer circuit is configured such that the data address to be written to is present in the FIFO and can be viewed in advance.
4. The pipeline Tile address conflict processing circuit of the graphics processor of claim 3, wherein the Tile information cache circuit is configured to cache 32 queues, each queue is 2 in depth, 2 conflict addresses can be suspended, 64 Tile requests can be cached in total, the addresses and the tag bits are stored by using a register, and the data is stored by using RAM.
5. The pipeline Tile address conflict processing circuit of the graphics processor of claim 4, wherein the Tile write judging circuit is used for judging the position of data written into the conflict cache, comparing the written data address with the address in the register, reading out the data from the FIFO if the queue can be written, then writing the data into the appointed position in the queue, and finishing data updating in the RAM.
6. The pipeline Tile address conflict processing circuit of the graphic processor according to claim 5, wherein in the Tile write judging circuit, write positions are divided into two types, one type is write of the same address, the other type is write of an empty queue, the write of the same address is the write of the same address, the position of the matching address is empty, the write of the empty queue is the write of no matching address, the write of the empty queue is the write of the empty queue, the write of the matching address is preferentially selected, when the matching address does not have empty or does not have the matching address and does not have the empty queue, blocking is formed, input Data is not read, cache queue write updating is performed, according to the write positions, a write queue needing to be updated is found, if vld0 is the position of the priority write, vld0 is marked as 1, and priority is marked as 0, and if the position of the Data write 0 is not marked as 1, and if the position of the Data write 1 is marked as 1.
7. A method of using the pipeline Tile address conflict handling circuit of the graphics processor of claim 1, the method comprising the steps of: 1) The data address to be written exists in the Tile input data FIFO buffer circuit and can be checked in advance; 2) The buffer design of the Tile information buffer circuit adopts 32 queues, each queue has 2 depth, 2 conflict addresses can be suspended, 64 Tile requests can be buffered in total, the addresses and the mark bits are stored by adopting a register, and the data are stored by adopting a RAM; 3) The Tile writing judging circuit compares the written data address with the address in the register, if the queue can be written, the data is read out from the FIFO, then written into the appointed position in the queue, and the data updating in the RAM is completed; The writing position is divided into two types, wherein one type is writing of the same address and the other type is writing of an empty queue, the writing of the same address is writing of the same address, the position of the matching address is provided with a vacancy, the writing of the empty queue is writing of the empty queue, no matching address is provided with an empty queue, the writing of the matching address is preferentially selected, when the matching address is not provided with a vacancy or the matching address is not provided with an empty queue, blocking is formed, input Data is not read, the writing of the cache queue is updated, namely, the writing queue which needs to be updated is found according to the writing position, if vld0 is 0, the position which is preferentially written into vld0 is marked as 1, the priority is marked as 0, and the Data is written into the position of Data0, otherwise, the position of vld1 is marked as 1, and the priority is marked as 1, and the Data is written into the position of Data 1; 4) The polling starts to select from the maximum position, reduces 1 each time until reducing to 0, and regains the maximum value; if the matching address is written in the process, the address is directly set as the position where the matching address is located, one of the two positions is selected according to the priority marking bit to be output, the queues are divided into 8 groups according to the sequence from 0 to 31 when the maximum value is selected, each group comprises four queues, one of the four queues is valid and is regarded as the group to be valid, the maximum value of the eighth group is 31, the maximum value of the seventh group is 27. 5) The Tile address conflict detection circuit monitors pixel addresses of all pipeline data processing paths, if the current input Tile and the monitored Tile coordinates are the same, the feedback conflict signal is used for reserving data in the cache, otherwise, the information cache queue is cleared; The method comprises the steps of comparing an input Tile address with a Tile address to be monitored in a pipeline, dividing a comparison circuit into four parts for circuit time sequence consideration, namely pipeline 1 address comparison, pipeline 2 address comparison, pipeline 3 address comparison and pipeline 4 address comparison, outputting each part by adopting a trigger, and finally merging and outputting the results of the four parts, wherein a time period is used by a Tile address conflict detection circuit, a conflict signal is provided for a conflict buffer unit of the previous stage to be used and used as a switching signal for outputting data by the unit, and outputting data is invalid and discarded when the conflict signal is valid.

Description

Pipeline Tile address conflict processing circuit and method of graphics processor Technical Field The invention belongs to the technical field of computer hardware, and particularly relates to a pipeline Tile address conflict processing circuit and method of a graphics processor. Background In a computer graphics processor, data processing is performed in a pipeline mode, when a plurality of pipelines are simultaneously used for parallel processing, when data with the same address exist in the pipelines, the problem of consistency of the data processing exists among the pipelines, and in order to avoid graphics drawing errors caused by the problem, a conflict detection unit is designed at an input port of the data, so that the data with the same address cannot enter the pipeline. Meanwhile, in order to ensure the processing speed and improve the design performance, when the same address appears, data is cached, so that the subsequent non-conflict address is issued, and blocking is not formed. The feasible basis of this cache design is that there is no data correlation between different addresses. Disclosure of Invention In order to solve the technical problems in the background technology, the invention provides a pipeline Tile address conflict processing circuit and method of a graphic processor, which adopts a FIFO input interface, has clear interface and time sequence, is easy to integrate, and greatly improves the graphic processing performance of a drawing scene when a conflict address and a non-conflict address exist simultaneously. The invention provides a pipeline Tile address conflict processing circuit of a graphic processor, which is characterized by comprising a Tile input data FIFO buffer circuit, a Tile writing judging circuit, a Tile information buffer circuit, a Tile output selecting circuit and a Tile address conflict detecting circuit, wherein the Tile input data FIFO buffer circuit is respectively connected with the Tile writing judging circuit and the Tile information buffer circuit, the Tile writing judging circuit is connected with the Tile information buffer circuit, the Tile information buffer circuit is connected with the Tile address conflict detecting circuit through the Tile output selecting circuit, and the Tile address conflict detecting circuit is connected with the Tile information buffer circuit. Further, the Tile information buffer circuit comprises a register and a RAM, the Tile writing judging circuit is connected with the register, the register is connected with the RAM, the RAM is connected with the Tile output selecting circuit, the Tile input data FIFO buffer circuit is connected with the RAM, and the Tile address conflict detecting circuit is connected with the register. Further, the data address to be written in the Tile input data FIFO buffer circuit exists in the FIFO and can be checked in advance. Furthermore, the buffer design of the Tile information buffer circuit adopts 32 queues, each queue has 2 depth, 2 conflict addresses can be suspended, 64 Tile requests can be buffered in total, the addresses and the tag bits are stored by adopting a register, and the data are stored by adopting a RAM. And comparing the written data address with the address in the register, reading the data from the FIFO if the queue can be written, writing the data into the designated position in the queue, and finishing data updating in the RAM. Further, in the rule writing judging circuit, writing positions are divided into two types, wherein one type is writing of the same address, the other type is writing of an empty queue, writing of the same address is that a matching address exists, a vacancy exists in the position of the matching address, writing of the empty queue is that no matching address exists, writing of the matching address is preferentially selected, blocking is formed when no vacancy exists in the matching address or the matching address exists and the empty queue exists, input Data is not read, writing updating of a cache queue is performed, namely a writing queue which needs to be updated is found according to the writing position, if vld0 is 0, the position which is preferentially written into vld0 is marked as 1, the priority is marked as 0, the position of Data is written into Data0, otherwise, the position of the Data is marked as 1, and the priority is written into the position of Data 1. Further, the Tile output selection circuit selects and outputs data in the data cache queue according to a mode of packet round-robin priority conflict address, wherein the data is selected from the maximum position, 1 is subtracted each time until the data is subtracted to 0, the maximum value is obtained again, if the matching address is written in the process, the address is directly set to the position where the matching address is located, one of the two positions is selected again according to priority mark bits for output at the selected position, the queues are divide