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CN-115393169-B - GlDrawBuffer-based one-to-many fragment mapping method and system in graphics processor

CN115393169BCN 115393169 BCN115393169 BCN 115393169BCN-115393169-B

Abstract

The invention relates to a one-to-many fragment mapping method and a system based on glDrawBuffer in a graphics processor. The method comprises the following steps of 1) identifying glDrawBuffer configured buffer areas, 2) sequencing the writing sequence of the buffer areas and generating buffer area indexes, 3) mapping fragments into different buffer areas in sequence according to the determined sequence, realizing the fragment output process by adopting a control state machine, sending received tiles for multiple times, and carrying different buffer area index information each time. The invention has the advantages of high fragment processing speed, circuit time sequence realization, clear circuit structure and improvement of the processing speed of the multi-buffer zone drawing scene.

Inventors

  • ZHANG SHU
  • TIAN ZE
  • DU QINQIN
  • LI PAN
  • WANG WEI

Assignees

  • 西安翔腾微电子科技有限公司

Dates

Publication Date
20260508
Application Date
20220820

Claims (7)

  1. 1. A method for one-to-many fragment mapping based on glDrawBuffer in a graphics processor, the method comprising the steps of: 1) Identifying glDrawBuffer configured buffers; Firstly calculating glDrawBuffer the sum of numbers with a configuration register gldrawbf of 1, then decoding according to the sum to generate a single hot code of 6bits, wherein bit0 effectively represents write 1 time of data, bit1 effectively represents write 2 times of data, bit3 effectively represents write 3 times of data, bit4 effectively represents write 4 times of data, bit5 effectively represents write 5 times of data, bit6 effectively represents write 6 times of data, all 0 represents no write, when the sum is 0, the method does not write any color buffer zone, at the moment, whether a depth test or a template test needs to be started or not is judged, if any one of the depth test or the template test needs to be started, the depth buffer zone to be written is represented, the number of times of transmission needs to be selected according to the configuration parameter which is not zero last time, if the buffer zone is configured to write left and right buffer zones simultaneously, the left and right times of writing are needed, and otherwise, the method only writes once; 2) Sequencing the writing sequence of the buffer areas and generating buffer area indexes; 3) And mapping the fragments into different buffer areas in turn according to the determined sequence, wherein the fragment output process is realized by adopting a control state machine, and the received tile is sent for multiple times, and different buffer area index information is carried each time.
  2. 2. The method of glDrawBuffer based one-to-many fragment mapping of claim 1, wherein the buffer index generated in step 2) is: Writing a buffer area index variable index6, wherein the index variable index is RAU when the transmission time is 6, and is invalid under other conditions; Writing a buffer index variable index5, namely, an LAU when the transmission time is6, an LAU when the transmission time is 5 and gldrawbf parameters are 6'b01xxxx, and an RAU when the transmission time is 5 and gldrawbf parameters are 6' b1 xxxx; Writing a buffer index variable index4, namely RB when gldrawbf parameters are 6' bxx1111, LAU when the transmission times are 5 and gldrawbf parameters are 6' b11xx, and RAU when the transmission times are 4 and gldrawbf parameters are 6' b01 xx; Writing a buffer index variable index3, namely LB when gldrawbf parameters are 6'bxxx111, RB when the transmission time is 3 and gldrawbf parameters are 6' b001xxx, RB when the transmission time is 4 and gldrawbf parameters are 6'b 0110 xxx, RB when the transmission time is 4 and gldrawbf parameters are 6' b101xxx, RB when the transmission time is 5 and gldrawbf parameters are 6'b111xxx, LAU when the transmission time is 3 and gldrawbf parameters are 6' b01xxx, LAU when the transmission time is 4 and gldrawbf parameters are 6'b11xxx, and RAU when the transmission time is 3 and gldrawbf parameters are 6' b1 xxxxx; Writing buffer index variable index2, RF when gldrawbf parameter is 6'bxxxx11, LB when gldrawbf parameter is 6' bxxxx 110, LB when gldrawbf parameter is 6'bxxxx 101, RB when transmission time is 2 and gldrawbf parameter is 6' bxxx001xxx, RB when transmission time is 3 and gldrawbf parameter is 6'b101xxx, RB when transmission time is 3 and gldrawbf parameter is 6' b 0110 xxx, RB when transmission time is 4 and gldrawbf parameter is 6'b111xxx, LAU when transmission time is 2 and gldrawbf parameter is 6' b01xxxx, LAU when transmission time is 3 and gldrawbf parameter is 6'b11xxxx, RAU when transmission time is 2 and gldrawbf parameter is 6' b1 xxxx; The write buffer index variable index1 is LF when gldrawbf parameter is 6'bxxx1, RF when gldrawbf parameter is 6' bxxx10, LB when gldrawbf parameter is 6'bxxx100, RB when gldrawbf parameter is 6' bxx1000, LAU when gldrawbf parameter is 6'bx10000, and RAU when gldrawbf parameter is 6' b 100000.
  3. 3. The method of claim 2, wherein the state machine in step 3) includes 7 states of IDLE state, SEND1 state, SEND2 state, SEND3 state, SEND4 state, SEND5 state, and SEND6 state, and the state jump procedure is as follows: 1) IDLE state: When the circuit is powered on and reset, the state machine is in the state, after reset and cancel, the input data is detected to be valid, 1 time of data is required to be issued, the state machine jumps to the SEND1 state, the data is issued, the 1 st write address index1 is issued, and the output ready signal is equal to the input ready signal; the input data is valid, 2 times of data are required to be issued, and the state machine jumps to the SEND2 state, issues the data, the 2 nd write address index2, and outputs a ready signal '0'; the input data is valid, 3 times of data are required to be issued, and the state machine jumps to the SEND3 state, and issues the data, the 3 rd write address index3 and outputs a ready signal '0'; The input data is valid, 4 times of data are required to be issued, and the state machine jumps to the SEND4 state, issues the data, 4 th write address index4, and outputs a ready signal '0'; The input data is valid, 5 times of data are required to be issued, and the state machine jumps to the SEND5 state, issues the data, the 5 th write address index5, and outputs a ready signal '0'; the input data is valid, 6 times of data are required to be issued, and the state machine jumps to the SEND6 state, issues the data, the 6 th write address index6 and outputs a ready signal '0'; Otherwise, the IDLE state is maintained, and the ready signal is output as '1'; 2) SEND1 state: the data can be issued, the input data is invalid, and the state machine jumps to the IDLE state, and the data is issued, the 1 st write address index1 and the ready signal is output as '1'; the input data is valid, 2 times of data are required to be issued, and the state machine jumps to the SEND2 state, issues the data, the 2 nd write address index2, and outputs a ready signal '0'; the input data is valid, 3 times of data are required to be issued, and the state machine jumps to the SEND3 state, and issues the data, the 3 rd write address index3 and outputs a ready signal '0'; The input data is valid, 4 times of data are required to be issued, and the state machine jumps to the SEND4 state, issues the data, 4 th write address index4, and outputs a ready signal '0'; The input data is valid, 5 times of data are required to be issued, and the state machine jumps to the SEND5 state, issues the data, the 5 th write address index5, and outputs a ready signal '0'; the input data is valid, 6 times of data are required to be issued, and the state machine jumps to the SEND6 state, issues the data, the 6 th write address index6 and outputs a ready signal '0'; 3) SEND2 state: The data can be issued, the state machine jumps to the SEND1 state, the data is issued, the 1 st write address indexes index1, and the output ready signal is equal to the input ready signal; 4) SEND3 state: The data can be issued, the state machine jumps to the SEND2 state, and the data and the 2 nd write address index2 are issued; 5) SEND4 state: The data can be issued, the state machine jumps to the SEND3 state, and the data and the 3 rd write address index3 are issued; 6) SEND5 state: The data can be issued, the state machine jumps to the SEND4 state, and the data and the 4 th write address index4 are issued; 7) SEND6 state: the data can be issued, the state machine jumps to the SEND5 state, and the data is issued, the 5 th write address index5.
  4. 4. A system for realizing a one-to-many fragment mapping method based on glDrawBuffer in a graphic processor is characterized in that the system comprises a glDrawBuffer parameter analysis module, a buffer index generation module and a fragment mapping module, wherein the glDrawBuffer parameter analysis module and the buffer index generation module are respectively connected with the fragment mapping module, the glDrawBuffer parameter analysis module analyzes a bufs value and determines a written buffer and the number of times of data transmission, the glDrawBuffer parameter analysis module firstly calculates glDrawBuffer configuration registers gldrawbf as the sum of 1 numbers, then decodes according to the sum to generate a single thermal code of 6bits, wherein bit0 effectively represents data written 1 time, bit1 effectively represents data written 2 times, bit3 effectively represents data written 3 times, bit4 effectively represents data written 4 times, bit5 effectively represents data written 6 times, all 0 represents data not written at the moment, when the sum is 0, represents data not written in any color buffer, whether a test template is required to be started or not, and if any buffer is required to be configured to be opened for a left or a right, and if the buffer is required to be configured for zero, and if the buffer is required to be opened for the left or the right, the buffer is required to be configured for the right, and if the buffer is required to be opened for the depth is not required to be written for the right.
  5. 5. The one-to-many fragment mapping system of claim 4 wherein the buffer index generation module generates 6 buffer indexes based on gldrawbf signals and number of transmissions.
  6. 6. The one-to-many fragment mapping system of claim 5, wherein the buffer index generation module generates the buffer index by: Writing a buffer area index variable index6, wherein the index variable index is RAU when the transmission time is 6, and is invalid under other conditions; Writing a buffer index variable index5, namely, an LAU when the transmission time is6, an LAU when the transmission time is 5 and gldrawbf parameters are 6'b01xxxx, and an RAU when the transmission time is 5 and gldrawbf parameters are 6' b1 xxxx; Writing a buffer index variable index4, namely RB when gldrawbf parameters are 6' bxx1111, LAU when the transmission times are 5 and gldrawbf parameters are 6' b11xx, and RAU when the transmission times are 4 and gldrawbf parameters are 6' b01 xx; Writing a buffer index variable index3, namely LB when gldrawbf parameters are 6'bxxx111, RB when the transmission time is 3 and gldrawbf parameters are 6' b001xxx, RB when the transmission time is 4 and gldrawbf parameters are 6'b 0110 xxx, RB when the transmission time is 4 and gldrawbf parameters are 6' b101xxx, RB when the transmission time is 5 and gldrawbf parameters are 6'b111xxx, LAU when the transmission time is 3 and gldrawbf parameters are 6' b01xxx, LAU when the transmission time is 4 and gldrawbf parameters are 6'b11xxx, and RAU when the transmission time is 3 and gldrawbf parameters are 6' b1 xxxxx; Writing buffer index variable index2, RF when gldrawbf parameter is 6'bxxxx11, LB when gldrawbf parameter is 6' bxxxx 110, LB when gldrawbf parameter is 6'bxxxx 101, RB when transmission time is 2 and gldrawbf parameter is 6' bxxx001xxx, RB when transmission time is 3 and gldrawbf parameter is 6'b101xxx, RB when transmission time is 3 and gldrawbf parameter is 6' b 0110 xxx, RB when transmission time is 4 and gldrawbf parameter is 6'b111xxx, LAU when transmission time is 2 and gldrawbf parameter is 6' b01xxxx, LAU when transmission time is 3 and gldrawbf parameter is 6'b11xxxx, RAU when transmission time is 2 and gldrawbf parameter is 6' b1 xxxx; The write buffer index variable index1 is LF when gldrawbf parameter is 6'bxxx1, RF when gldrawbf parameter is 6' bxxx10, LB when gldrawbf parameter is 6'bxxx100, RB when gldrawbf parameter is 6' bxx1000, LAU when gldrawbf parameter is 6'bx10000, and RAU when gldrawbf parameter is 6' b 100000.
  7. 7. The one-to-many fragment mapping system of claim 6, wherein the fragment mapping module core is a state machine comprising 7 states of IDLE state, SEND1 state, SEND2 state, SEND3 state, SEND4 state, SEND5 state, SEND6 state, and wherein the state jump procedure is as follows: 1) IDLE state: When the circuit is powered on and reset, the state machine is in the state, after reset and cancel, the input data is detected to be valid, 1 time of data is required to be issued, the state machine jumps to the SEND1 state, the data is issued, the 1 st write address index1 is issued, and the output ready signal is equal to the input ready signal; the input data is valid, 2 times of data are required to be issued, and the state machine jumps to the SEND2 state, issues the data, the 2 nd write address index2, and outputs a ready signal '0'; the input data is valid, 3 times of data are required to be issued, and the state machine jumps to the SEND3 state, and issues the data, the 3 rd write address index3 and outputs a ready signal '0'; The input data is valid, 4 times of data are required to be issued, and the state machine jumps to the SEND4 state, issues the data, 4 th write address index4, and outputs a ready signal '0'; The input data is valid, 5 times of data are required to be issued, and the state machine jumps to the SEND5 state, issues the data, the 5 th write address index5, and outputs a ready signal '0'; the input data is valid, 6 times of data are required to be issued, and the state machine jumps to the SEND6 state, issues the data, the 6 th write address index6 and outputs a ready signal '0'; Otherwise, the IDLE state is maintained, and the ready signal is output as '1'; 2) SEND1 state: the data can be issued, the input data is invalid, and the state machine jumps to the IDLE state, and the data is issued, the 1 st write address index1 and the ready signal is output as '1'; the input data is valid, 2 times of data are required to be issued, and the state machine jumps to the SEND2 state, issues the data, the 2 nd write address index2, and outputs a ready signal '0'; the input data is valid, 3 times of data are required to be issued, and the state machine jumps to the SEND3 state, and issues the data, the 3 rd write address index3 and outputs a ready signal '0'; The input data is valid, 4 times of data are required to be issued, and the state machine jumps to the SEND4 state, issues the data, 4 th write address index4, and outputs a ready signal '0'; The input data is valid, 5 times of data are required to be issued, and the state machine jumps to the SEND5 state, issues the data, the 5 th write address index5, and outputs a ready signal '0'; the input data is valid, 6 times of data are required to be issued, and the state machine jumps to the SEND6 state, issues the data, the 6 th write address index6 and outputs a ready signal '0'; 3) SEND2 state: The data can be issued, the state machine jumps to the SEND1 state, the data is issued, the 1 st write address indexes index1, and the output ready signal is equal to the input ready signal; 4) SEND3 state: The data can be issued, the state machine jumps to the SEND2 state, and the data and the 2 nd write address index2 are issued; 5) SEND4 state: The data can be issued, the state machine jumps to the SEND3 state, and the data and the 3 rd write address index3 are issued; 6) SEND5 state: The data can be issued, the state machine jumps to the SEND4 state, and the data and the 4 th write address index4 are issued; 7) SEND6 state: the data can be issued, the state machine jumps to the SEND5 state, and the data is issued, the 5 th write address index5.

Description

GlDrawBuffer-based one-to-many fragment mapping method and system in graphics processor Technical Field The present invention relates to the field of computer hardware, and in particular, to a method and a system for mapping one to more fragments based on glDrawBuffer in a graphics processor. Background In computer graphics processing and computer graphics, a fragment is data that is ultimately written into a frame buffer for graphical display. In the segment processing stage, the segment needs to perform a series of operations with the data in the frame buffer, and when the buffer to which the segment is finally written is different, the operation data and the operation result of the corresponding segment in the segment processing stage are different. The frame buffer to be written is specified by the graphics parameter configuration command glDrawBuffer, and the number of buffers to be written for configuring a fragment can be 1 to a plurality of, so that the fragment needs to be split into a plurality of fragments for processing according to different frame buffer configurations. Disclosure of Invention In order to solve the technical problems in the background technology, the invention provides a one-to-many fragment mapping method and a system based on glDrawBuffer in a graphics processor, which have the advantages of high fragment processing speed, convenience for realizing circuit time sequence, clear circuit structure and improvement of the processing speed of a multi-buffer zone drawing scene. The technical proposal of the invention is that the invention is a one-to-many fragment mapping method based on glDrawBuffer in a graphics processor, which is characterized in that the method comprises the following steps: 1) Identifying glDrawBuffer configured buffers; 2) Sequencing the writing sequence of the buffer areas and generating buffer area indexes; 3) And mapping the fragments into different buffer areas in turn according to the determined sequence, wherein the fragment output process is realized by adopting a control state machine, and the received tile is sent for multiple times, and different buffer area index information is carried each time. Further, the specific steps of the step 1) are that firstly, glDrawBuffer configuration registers gldrawbf are calculated as the sum of numbers of 1, then decoding is carried out according to the sum to generate a single hot code of 6bits, wherein bit0 effectively represents writing 1 time of data, bit1 effectively represents writing 2 times of data, bit3 effectively represents writing 3 times of data, bit4 effectively represents writing 4 times of data, bit5 effectively represents writing 5 times of data, bit6 effectively represents writing 6 times of data, all 0's represent no writing, when the sum is 0, no writing is represented, at the moment, whether a depth test or a template test needs to be started or not is judged, if any one of the depth buffers is started, the sending times need to be selected according to the configuration parameters which are not zero last time, if the buffer is configured to be simultaneously written with the left buffer and the right buffer, the writing is needed to be left and right twice, otherwise, the buffer is only written once. Further, the buffer index generated in step 2) is: Writing a buffer area index variable index6, wherein the index variable index is RAU when the transmission time is 6, and is invalid under other conditions; Writing a buffer index variable index5, namely, an LAU when the transmission time is6, an LAU when the transmission time is 5 and gldrawbf parameters are 6'b01xxxx, and an RAU when the transmission time is 5 and gldrawbf parameters are 6' b1 xxxx; Writing a buffer index variable index4, namely RB when gldrawbf parameters are 6' bxx1111, LAU when the transmission times are 5 and gldrawbf parameters are 6' b11xx, and RAU when the transmission times are 4 and gldrawbf parameters are 6' b01 xx; Writing a buffer index variable index3, namely LB when gldrawbf parameters are 6'bxxx111, RB when the transmission time is 3 and gldrawbf parameters are 6' b001xxx, RB when the transmission time is 4 and gldrawbf parameters are 6'b 0110 xxx, RB when the transmission time is 4 and gldrawbf parameters are 6' b101xxx, RB when the transmission time is 5 and gldrawbf parameters are 6'b111xxx, LAU when the transmission time is 3 and gldrawbf parameters are 6' b01xxx, LAU when the transmission time is 4 and gldrawbf parameters are 6'b11xxx, and RAU when the transmission time is 3 and gldrawbf parameters are 6' b1 xxxxx; Writing buffer index variable index2, RF when gldrawbf parameter is 6'bxxxx11, LB when gldrawbf parameter is 6' bxxxx 110, LB when gldrawbf parameter is 6'bxxxx 101, RB when transmission time is 2 and gldrawbf parameter is 6' bxxx001xxx, RB when transmission time is 3 and gldrawbf parameter is 6'b101xxx, RB when transmission time is 3 and gldrawbf parameter is 6' b 0110 xxx, RB when transmission