CN-115411052-B - Semiconductor structure, forming method thereof, circuit and circuit working method

Abstract

A semiconductor structure and a forming method thereof are provided, the structure comprises a substrate, a first grid electrode structure and a first channel region, wherein the first grid electrode structure and the first channel region are arranged on the first well region, the first channel region is arranged in the first well region at the bottom of the first grid electrode structure, the conductivity type of the first channel region is the same as that of the first well region, a second grid electrode structure, a second channel region and a second source region and a second drain region are arranged on the second well region, the second source region and the second drain region are arranged in the second well region at the two sides of the second grid electrode structure, the second channel region is arranged in the second well region at the bottom of the second grid electrode structure, the conductivity type of the second channel region is opposite to that of the second well region, the second source region and the second drain region are electrically interconnected with the first well region, and the second source region and the first drain region are electrically interconnected. The performance of the semiconductor structure formed by the method is improved.

Inventors

• TANG FEI

Assignees

• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(北京)有限公司
• 中芯国际集成电路制造(北京)有限公司

Dates

Publication Date

20260421

Application Date

20210510

Priority Date

20210510

Claims (20)

1. 1. A semiconductor structure, comprising: A substrate comprising a first well region and a second well region; a first gate structure and a first channel region on the first well region, and a first source region and a first drain region in the first well region on both sides of the first gate structure, the first channel region being in the first well region at the bottom of the first gate structure, the first channel region has the same conductivity type as the first well region, the first source region and the first drain region have opposite conductivity types to the first well region, and the first gate structure comprises a gate dielectric layer and a gate layer positioned on the gate dielectric layer; The second gate structure is positioned on the second well region, the second channel region is positioned in the second well region at the bottom of the second gate structure, the second channel region is positioned between the second source region and the second drain region, the conductivity type of the second channel region is opposite to that of the second well region, the conductivity types of the second source region and the second drain region are the same as those of the second channel region, the second drain region is electrically connected with the first gate structure, the second gate structure is in contact with the second channel region, and doped ions are arranged in the second gate structure, and the conductivity types of the doped ions are opposite to those of the second channel region; And the second source region and the first well region are electrically interconnected through the first connecting region.
2. 2. The semiconductor structure of claim 1, wherein the first well region has a conductivity type that is the same as a conductivity type of the second well region, and wherein the second source region and the second drain region have a conductivity type that is the same as a conductivity type of the first source region and the first drain region.
3. 3. The semiconductor structure of claim 1, wherein the first well region has a conductivity type opposite to a conductivity type of the second well region, and wherein the second source region and the second drain region have a conductivity type opposite to a conductivity type of the first source region and the first drain region.
4. 4. The semiconductor structure of claim 1, wherein the substrate comprises a base and a fin structure on the base, the fin structure comprising a first fin in a first well region and a second fin in a second well region, the first gate structure crossing the first fin, the second gate structure crossing the second fin.
5. 5. The semiconductor structure of claim 4, wherein the first fin has anti-punch-through ions therein, the anti-punch-through ions having a conductivity type that is the same as a conductivity type of the first well region.
6. 6. The semiconductor structure of claim 1, wherein a conductivity type of the first connection region is the same as a conductivity type of the first well region, and an ion concentration within the first connection region is greater than an ion concentration within the first well region.
7. 7. The semiconductor structure of claim 1, further comprising a first conductive structure and a second conductive structure on the substrate, the first conductive structure electrically interconnecting the second drain region and the first gate structure, the second conductive structure electrically interconnecting the second source region and the first connection region.
8. 8. The semiconductor structure of claim 7, wherein the second conductive structure is further electrically connected to the first source region.
9. 9. The semiconductor structure of claim 7, further comprising a second connection region on a surface of the second well region, the second gate structure and the second well region being electrically connected by the second connection region.
10. 10. The semiconductor structure of claim 9, wherein a conductivity type of the second connection region is the same as a conductivity type of the second well region, and an ion concentration in the second connection region is greater than an ion concentration in the second well region.
11. 11. The semiconductor structure of claim 9, further comprising a third conductive structure on the substrate, the third conductive structure electrically connecting the second gate structure and the second connection region.
12. 12. The semiconductor structure of claim 11, further comprising a dielectric structure on the substrate, the first gate structure and the second gate structure being located within the dielectric structure, the first conductive structure, the second conductive structure, and the third conductive structure being located within the dielectric structure.
13. 13. The semiconductor structure of claim 1, wherein the material of the gate dielectric layer comprises a high dielectric constant material having a dielectric constant greater than 3.9, the high dielectric constant material comprising aluminum oxide or hafnium oxide, the material of the gate layer comprising a metal comprising tungsten.
14. 14. The semiconductor structure of claim 13, wherein the first gate structure further comprises a work function layer, the work function layer being located between the gate dielectric layer and the gate layer, the work function layer material comprising an N-type work function material comprising titanium aluminum or a P-type work function material comprising titanium nitride or tantalum nitride.
15. 15. The semiconductor structure of claim 1, wherein a material of the second gate structure comprises silicon.
16. 16. The semiconductor structure of claim 1, wherein the first well region has a conductivity type of N-type or P-type, the second well region has a conductivity type of N-type or P-type, the N-type ions comprise phosphorus ions, arsenic ions, or antimony ions, and the P-type ions comprise boron ions, boron fluoride ions, or indium ions.
17. 17. A method of forming a semiconductor structure, comprising: Providing a substrate, wherein the substrate comprises a first well region and a second well region; Forming a first gate structure and a first channel region on the first well region, wherein the first channel region is positioned in the first well region at the bottom of the first gate structure, the conductivity type of the first channel region is the same as that of the first well region, and the first gate structure comprises a gate dielectric layer and a gate layer positioned on the gate dielectric layer; Forming a second gate structure, a second channel region, a second source region and a second drain region in the second well region at two sides of the second gate structure, wherein the second channel region is positioned in the second well region at the bottom of the second gate structure, the second channel region is positioned between the second source region and the second drain region, the conductivity type of the second channel region is opposite to that of the second well region, the conductivity types of the second source region and the second drain region are the same as those of the second channel region, the second drain region and the first gate structure are electrically interconnected, the second gate structure is in contact with the second channel region, and doped ions are arranged in the second gate structure, and the conductivity type of the doped ions is opposite to that of the second channel region; and forming a first connecting region on the surface of the first well region, wherein the second source region and the first well region are electrically interconnected through the first connecting region.
18. 18. The method of forming a semiconductor structure as claimed in claim 17, wherein forming the first gate structure on the first well region further comprises forming a first source region and a first drain region in the first well region on opposite sides of the first gate structure, the first source region and the first drain region having a conductivity type opposite to a conductivity type of the first channel region.
19. 19. The method of forming a semiconductor structure as claimed in claim 18, wherein the first well region has a conductivity type that is the same as a conductivity type of the second well region, and wherein the second source region and the second drain region have a conductivity type that is the same as a conductivity type of the first source region and the first drain region.
20. 20. The method of forming a semiconductor structure of claim 19, wherein the second source region and the second drain region are formed simultaneously with the first source region and the first drain region.

Description

Semiconductor structure, forming method thereof, circuit and circuit working method Technical Field The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure, a method for forming the same, a circuit and a circuit operating method. Background The main devices of integrated circuits, especially very large scale integrated circuits, are Metal-Oxide-semiconductor field effect transistors (MOS transistors). Since the invention of a MOS transistor, the geometric dimension is continuously reduced according to the Moore's law, the development of the characteristic dimension is now in the 45 nanometer range, at this scale, various secondary effects caused by the physical limit of the device are gradually unavoidable, and the characteristic dimension of the device is becoming more and more difficult to scale down. Among them, in the field of MOS transistor devices and circuit fabrication thereof, the most challenging is the problem of leakage current from the gate to the substrate due to the reduction of the polysilicon or gate dielectric layer thickness in the device scaling process of the conventional CMOS process. Therefore, the problem of leakage current of the gate to the substrate is a problem that needs to be continuously solved. Disclosure of Invention The technical problem solved by the invention is that the technical scheme of the invention provides a semiconductor structure, a forming method, a circuit and a circuit working method thereof, so as to improve the performance of the semiconductor structure. In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure, which comprises a substrate, a first grid structure and a first channel region, a second grid structure, a second channel region, a second source region and a second drain region, wherein the substrate comprises a first well region and a second well region, the first grid structure and the first channel region are arranged on the first well region, the first channel region is arranged in the first well region at the bottom of the first grid structure, the conductivity type of the first channel region is the same as that of the first well region, the second grid structure and the second channel region are arranged on the second well region, the second source region and the second drain region are arranged in the second well region at the two sides of the second grid structure, the second channel region is arranged in the second well region at the bottom of the second grid structure, the second channel region is arranged between the second source region and the second drain region, the conductivity type of the second channel region is opposite to that of the second well region, the second source region and the second drain region are the same as that of the second channel region, the second source region and the first grid structure are electrically interconnected, and the first source region and the second drain region are arranged on the surface of the first well region, and the first junction region are electrically connected through the first junction region. Optionally, the conductivity type of the first well region is the same as that of the second well region, and the conductivity type of the second source region and the second drain region is the same as that of the first source region and the first drain region. Optionally, the first well region has a conductivity type opposite to that of the second well region, and the second source region and the second drain region have a conductivity type opposite to that of the first source region and the first drain region. Optionally, the second gate structure has a doped ion therein, and a conductivity type of the doped ion is opposite to a conductivity type of the second channel region. The substrate comprises a substrate and a fin structure located on the substrate, wherein the fin structure comprises a first fin located in a first well region and a second fin located in a second well region, the first gate structure spans the first fin, and the second gate structure spans the second fin. Optionally, the first fin portion has an anti-punch-through ion therein, and a conductivity type of the anti-punch-through ion is the same as a conductivity type of the first well region. Optionally, the conductivity type of the first connection region is the same as the conductivity type of the first well region, and the ion concentration in the first connection region is greater than the ion concentration in the first well region. Optionally, a first conductive structure and a second conductive structure are located on the substrate, the first conductive structure electrically interconnects the second drain region and the first gate structure, and the second conductive structure electrically interconnects the second source region and the first connection region. Optionally, the second con