CN-115412069-B - Comparator and decision feedback equalization circuit

Abstract

The application provides a comparator and a decision feedback equalization circuit, wherein the comparator comprises a first input circuit, a second input circuit and a second positive feedback circuit, wherein the first input circuit is provided with two pairs of pipes, the types of the two pairs of pipes are different, the two pairs of pipes are used for receiving a first input signal and a first reference signal, the two pairs of pipes are also used for generating a first differential signal according to the first input signal and the first reference signal in a sampling stage, the first positive feedback circuit is used for accelerating the difference value between the first differential signal, the second input circuit is provided with two pairs of pipes, the types of the two pairs of pipes are different, the two pairs of pipes are used for receiving a second input signal and a second reference signal, the second positive feedback circuit is also used for generating a second differential signal according to the second input signal and the second reference signal in the sampling stage, the second positive feedback circuit is used for accelerating the difference value between the second differential signal, and the output circuit is used for amplifying and latching the voltage signal at the output end of the first input circuit in a regenerating stage, and outputting a comparison result.

Inventors

• Gu yinchuan

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260508

Application Date

20210527

Claims (20)

1. 1. A decision feedback equalization circuit is characterized by comprising four comparators, which are sequentially marked as a first comparator, a second comparator, a third comparator and a fourth comparator; Each comparator is provided with four input ends and two output ends, and comprises: The first input circuit is provided with two geminate transistors, the types of the two geminate transistors are different, the control ends of the two geminate transistors are used as the input ends of the comparator, the two geminate transistors are used for receiving a first input signal and a first reference signal, and the first input circuit is also used for generating a first differential signal according to the first input signal and the first reference signal in a sampling stage; The first positive feedback circuit is connected with the output end of the first input circuit and is used for accelerating the difference value between the first differential signals; The second input circuit is provided with two geminate transistors, the types of the two geminate transistors are different, the control ends of the two geminate transistors are used as the input ends of the comparator, the two geminate transistors are used for receiving a second input signal and a second reference signal, and the second input circuit is also used for generating a second differential signal according to the second input signal and the second reference signal in a sampling stage; The second positive feedback circuit is connected with the output end of the second input circuit and is used for accelerating the difference value between the second differential signals; The output circuit is provided with an input end and an output end, the output end is the output end of the comparator, the input end of the output circuit is connected with the output end of the first input circuit, and the output circuit is used for amplifying and latching the voltage signal of the output end of the first input circuit and the voltage signal of the output end of the second input circuit in the regeneration stage so as to output a comparison result; the first comparator is provided with a first input end for receiving a first input signal, a second input end for receiving a first reference signal, a third input end directly connected with the first output end of the fourth comparator for receiving a second input signal, and a fourth input end directly connected with the second output end of the fourth comparator for receiving a second input signal; the first input end of the second comparator is used for receiving a first input signal, the second input end of the second comparator is used for receiving a first reference signal, the third input end of the second comparator is directly connected with the first output end of the first comparator and used for receiving a second input signal, and the fourth input end of the second comparator is directly connected with the second output end of the first comparator and used for receiving a second input signal; The first input end of the third comparator is used for receiving a first input signal, the second input end of the third comparator is used for receiving a first reference signal, the third input end of the third comparator is directly connected with the first output end of the second comparator and used for receiving a second input signal, and the fourth input end of the third comparator is directly connected with the second output end of the second comparator and used for receiving a second input signal; The first input end of the fourth comparator is used for receiving a first input signal, the second input end of the fourth comparator is used for receiving a first reference signal, the third input end of the fourth comparator is directly connected with the first output end of the third comparator and used for receiving a second input signal, and the fourth input end of the fourth comparator is directly connected with the second output end of the third comparator and used for receiving a second input signal.
2. 2. The decision feedback equalization circuit of claim 1, wherein said first positive feedback circuit comprises: the first feedback module is connected with the output end of the first input circuit and is used for pulling the voltage of the output end of the first input circuit to achieve the purpose of accelerating the difference value between the first differential signals; And the second feedback module is connected with the output end of the first input circuit and is used for pulling the voltage of the output end of the first input circuit to realize the acceleration of the difference value between the first differential signals.
3. 3. The decision feedback equalizer circuit of claim 2, wherein the first input circuit has two outputs; the first feedback module includes: The control end of the first feedback unit is connected with the first output end of the first input circuit, the first end of the first feedback unit is connected with the second output end of the first input circuit, and the first feedback unit is used for pulling the voltage of the second output end of the first input circuit according to the voltage of the first output end of the first input circuit; the control end of the second feedback unit is connected with the second output end of the first input circuit, and the first end of the second feedback unit is connected with the first output end of the first input circuit and is used for pulling the voltage of the first output end of the first input circuit according to the voltage of the second output end of the first input circuit; the second feedback module includes: the control end of the third feedback unit is connected with the first output end of the first input circuit, the first end of the third feedback unit is connected with the second output end of the first input circuit, and the third feedback unit is used for pulling the voltage of the second output end of the first input circuit according to the voltage of the first output end of the first input circuit; and the control end of the fourth feedback unit is connected with the second output end of the first input circuit, and the first end of the fourth feedback unit is connected with the first output end of the first input circuit and is used for pulling the voltage of the first output end of the first input circuit according to the voltage of the second output end of the first input circuit.
4. 4. A decision feedback equalizer circuit as claimed in claim 3, wherein: the first feedback unit comprises a first feedback transistor, a second feedback transistor and a first feedback control unit, wherein the control end of the first feedback transistor is the control end of the first feedback unit, and the second end of the first feedback transistor is the first end of the first feedback unit; The second feedback unit comprises a second feedback transistor, a first feedback unit and a second feedback unit, wherein the control end of the second feedback transistor is the control end of the second feedback unit, and the second end of the second feedback transistor is the first end of the second feedback unit; The third feedback unit comprises a third feedback transistor, a first feedback unit and a second feedback unit, wherein the control end of the third feedback transistor is the control end of the third feedback unit, and the first end of the third feedback transistor is the first end of the third feedback unit; The fourth feedback unit comprises a fourth feedback transistor, wherein the control end of the fourth feedback transistor is the control end of the fourth feedback unit, and the first end of the fourth feedback transistor is the first end of the fourth feedback unit.
5. 5. The decision feedback equalizer circuit of claim 4, wherein the first input circuit comprises: The control end of the first input transistor is used for receiving the first input signal, the second end of the first input transistor is used as a first output end of the first input circuit, and the second end of the first input transistor is connected with the control end of the first feedback transistor and the second end of the second feedback transistor; the control end of the second input transistor is used for receiving the first reference signal, the second end of the second input transistor is used as the second output end of the first input circuit, and the second end of the second input transistor is connected with the control end of the second feedback transistor and the second end of the first feedback transistor; a third input transistor, a control end of which is used for receiving the first input signal, a first end of which is connected with a second end of the first input transistor, and a first end of which is connected with a control end of the third feedback transistor and a first end of the fourth feedback transistor; a control end of the fourth input transistor is used for receiving the first reference signal, a first end of the fourth input transistor is connected with a second end of the second input transistor, and a first end of the fourth input transistor is connected with a control end of the fourth feedback transistor and a first end of the third feedback transistor; And the control end of the fifth input transistor is used for receiving a clock signal, the first end of the fifth input transistor is connected with the second end of the third input transistor, the second end of the fourth input transistor, the second end of the third feedback transistor and the second end of the fourth feedback transistor, and the second end of the fifth input transistor is connected with the grounding end or the power supply end.
6. 6. The decision feedback equalization circuit of claim 1, wherein said second positive feedback circuit comprises: the third feedback module is connected with the output end of the second input circuit and is used for accelerating the difference value between the second differential signals by pulling the voltage of the output end of the second input circuit; And the fourth feedback module is connected with the output end of the second input circuit and is used for accelerating the difference value between the second differential signals by pulling the voltage of the output end of the second input circuit.
7. 7. The decision feedback equalizer circuit of claim 6, wherein the second input circuit has two outputs; the third feedback module includes: A fifth feedback unit, the control end of which is connected with the first output end of the second input circuit, the first end of which is connected with the second output end of the second input circuit, and the fifth feedback unit is used for pulling the voltage of the second output end of the second input circuit according to the voltage of the first output end of the second input circuit; a sixth feedback unit, the control end of which is connected with the second output end of the second input circuit, and the first end of which is connected with the first output end of the second input circuit, and is used for pulling the voltage of the first output end of the second input circuit according to the voltage of the second output end of the second input circuit; the fourth feedback module includes: A seventh feedback unit, the control end of which is connected with the first output end of the second input circuit, the first end of which is connected with the second output end of the second input circuit, and the seventh feedback unit is used for pulling the voltage of the second output end of the second input circuit according to the voltage of the first output end of the second input circuit; And the control end of the eighth feedback unit is connected with the second output end of the second input circuit, and the first end of the eighth feedback unit is connected with the first output end of the second input circuit and is used for pulling the voltage of the first output end of the second input circuit according to the voltage of the second output end of the second input circuit.
8. 8. The decision feedback equalizer circuit of claim 7, wherein: The fifth feedback unit comprises a fifth feedback transistor, a first feedback unit and a second feedback unit, wherein the control end of the fifth feedback transistor is the control end of the fifth feedback unit, and the second end of the fifth feedback transistor is the first end of the fifth feedback unit; The sixth feedback unit comprises a sixth feedback transistor, wherein the control end of the sixth feedback transistor is the control end of the sixth feedback unit, and the second end of the sixth feedback transistor is the first end of the sixth feedback unit; the seventh feedback unit comprises a seventh feedback transistor, wherein the control end of the seventh feedback transistor is the control end of the seventh feedback unit, and the first end of the seventh feedback transistor is the first end of the seventh feedback unit; The eighth feedback unit comprises an eighth feedback transistor, wherein the control end of the eighth feedback transistor is the control end of the eighth feedback unit, and the first end of the eighth feedback transistor is the first end of the eighth feedback unit.
9. 9. The decision feedback equalizer circuit of claim 8, wherein the second input circuit comprises: a sixth input transistor, a control end of which is used for receiving the second input signal, a second end of which is used as a first output end of the second input circuit, and a second end of which is connected with the control end of the fifth feedback transistor and the second end of the sixth feedback transistor; a seventh input transistor, the control end of which is used for receiving the second reference signal, the second end of which is used as the second output end of the second input circuit, and the second end of which is connected with the control end of the sixth feedback transistor and the second end of the fifth feedback transistor; an eighth input transistor, a control end of which is used for receiving the second input signal, a first end of which is connected with a second end of the sixth input transistor, and a first end of which is connected with a control end of the seventh feedback transistor and a first end of the eighth feedback transistor; a ninth input transistor, a control end of which is used for receiving the second reference signal, a first end of which is connected with the second end of the seventh input transistor, and a first end of which is connected with the control end of the eighth feedback transistor and the first end of the seventh feedback transistor; and the control end of the tenth input transistor is used for receiving a clock signal, the first end of the tenth input transistor is connected with the second end of the eighth input transistor, the second end of the ninth input transistor, the second end of the seventh feedback transistor and the second end of the eighth feedback transistor, and the second end of the tenth input transistor is connected with the grounding end or the power supply end.
10. 10. The decision feedback equalizer circuit of claim 9, wherein: the first feedback transistor, the second feedback transistor, the fifth feedback transistor, the sixth feedback transistor, the first input transistor, the second input transistor, the sixth input transistor and the seventh input transistor are of the same type; The third feedback transistor, the fourth feedback transistor, the seventh feedback transistor, the eighth feedback transistor, the third input transistor, the fourth input transistor, the fifth input transistor, the eighth input transistor, the ninth input transistor, and the tenth input transistor are of the same type.
11. 11. The decision feedback equalizer circuit of claim 10, wherein: the first feedback transistor and the second feedback transistor have the same size, the first input transistor and the second input transistor have the same size, and the size of the first feedback transistor is smaller than one half of the size of the first input transistor; the third feedback transistor and the fourth feedback transistor have the same size, the third input transistor and the fourth input transistor have the same size, and the size of the third feedback transistor is smaller than one half of the size of the third input transistor; The size of the fifth feedback transistor is the same as that of the sixth feedback transistor, the size of the sixth input transistor is the same as that of the seventh input transistor, and the size of the fifth feedback transistor is less than half of that of the sixth input transistor; The size of the seventh feedback transistor is the same as that of the eighth feedback transistor, the size of the eighth input transistor is the same as that of the ninth input transistor, and the size of the seventh feedback transistor is less than one half of that of the eighth input transistor; the size of the sixth input transistor is less than one half of the size of the first input transistor; The size of the eighth input transistor is less than one half of the size of the third input transistor.
12. 12. The decision feedback equalizer circuit of claim 11, wherein: When the first feedback transistor, the second feedback transistor, the fifth feedback transistor, the sixth feedback transistor, the first input transistor, the second input transistor, the sixth input transistor and the seventh input transistor are P-type transistors, the source electrode of the P-type transistor is a first end, and the grid electrode of the P-type transistor is a control end; When the third feedback transistor, the fourth feedback transistor, the seventh feedback transistor, the eighth feedback transistor, the third input transistor, the fourth input transistor, the fifth input transistor, the eighth input transistor, the ninth input transistor and the tenth input transistor are N-type transistors, the drain electrode of the N-type transistor is a first end, and the grid electrode of the N-type transistor is a control end; Or alternatively When the first feedback transistor, the second feedback transistor, the fifth feedback transistor, the sixth feedback transistor, the first input transistor, the second input transistor, the sixth input transistor and the seventh input transistor are N-type transistors, the source electrode of the N-type transistor is a first end, and the grid electrode of the N-type transistor is a control end; when the third feedback transistor, the fourth feedback transistor, the seventh feedback transistor, the eighth feedback transistor, the third input transistor, the fourth input transistor, the fifth input transistor, the eighth input transistor, the ninth input transistor and the tenth input transistor are P-type transistors, the drain electrode of the P-type transistor is a first end, and the gate electrode of the P-type transistor is a control end.
13. 13. The decision feedback equalization circuit of claim 1, wherein the comparator further comprises: A first reset circuit connected between a first output terminal of the first input circuit and a second output terminal of the first input circuit, for resetting a voltage of the first output terminal of the first input circuit and a voltage of the second output terminal of the first input circuit; The second reset circuit is connected to the first output end of the output circuit and is used for resetting the voltage of the first output end of the output circuit; and the third reset circuit is connected to the second output end of the output circuit and is used for resetting the voltage of the second output end of the output circuit.
14. 14. The decision feedback equalization circuit of claim 13, wherein the first reset circuit comprises: A first clock control transistor, the control end of which receives a clock signal, and the second end of which is connected with the first output end of the first input circuit; the control end of the second clock control transistor receives the clock signal, the second end of the second clock control transistor is connected with the second output end of the first input circuit, and the first end of the second clock control transistor is connected with the first end of the first clock control transistor and then is grounded or connected with the power supply end; The second reset circuit comprises a third clock control transistor, a second end of which is connected with the first output end of the output circuit, wherein the control end of the third clock control transistor receives a clock signal; the third reset circuit comprises a fourth clock control transistor, wherein the control end of the fourth clock control transistor receives a clock signal, and the second end of the fourth clock control transistor is connected with the second output end of the output circuit.
15. 15. The decision feedback equalization circuit of claim 14, wherein the first clocked transistor, the second clocked transistor, the third clocked transistor, and the fourth clocked transistor are of the same type.
16. 16. The decision feedback equalization circuit of claim 1, wherein the output circuit comprises: A first output transistor, the second end of which is the first input end of the output circuit; a second output transistor, a second end of which is a second input end of the output circuit; the control end of the third output transistor is connected with the control end of the first output transistor, the control end of the third output transistor is also connected with the second end of the fourth output transistor, and the second end of the third output transistor is used as the first output end of the output circuit; and the control end of the fourth output transistor is connected with the control end of the second output transistor, the control end of the fourth output transistor is also connected with the second end of the third output transistor, and the second end of the fourth output transistor is used as the second output end of the output circuit.
17. 17. The decision feedback equalizer circuit of claim 16, wherein: If the first output transistor and the second output transistor are both N-type transistors, the drain electrode of the N-type transistor is a first end, and the grid electrode of the N-type transistor is a control end; If the third output transistor and the fourth output transistor are P-type transistors, the first clock control transistor to the fourth clock control transistor are P-type transistors, the source electrode of the P-type transistor is a first end, and the grid electrode of the P-type transistor is a control end; Or alternatively The first output transistor and the second output transistor are both P-type transistors, the drain electrode of each P-type transistor is a first end, and the grid electrode of each P-type transistor is a control end; the third output transistor and the fourth output transistor are N-type transistors, the first clock control transistor to the fourth clock control transistor are N-type transistors, the source electrode of the N-type transistor is a first end, and the grid electrode of the N-type transistor is a control end.
18. 18. The decision feedback equalizer circuit of claim 6, wherein: the third feedback module includes at least one first controllable feedback sub-module, each first controllable feedback sub-module including: A fifth feedback unit, the control end of which is connected with the first output end of the second input circuit through a first switch, and the first end of which is connected with the second output end of the second input circuit, and is used for pulling the voltage of the second output end of the second input circuit according to the voltage of the first output end of the second input circuit under the control of the first switch; A sixth feedback unit, the control end of which is connected with the second output end of the second input circuit through a second switch, and the first end of which is connected with the first output end of the second input circuit, and is used for pulling the voltage of the first output end of the second input circuit according to the voltage of the second output end of the second input circuit under the control of the second switch; The fourth feedback module includes at least one second controllable feedback sub-module, each second controllable feedback sub-module including: A seventh feedback unit, the control end of which is connected with the first output end of the second input circuit through a third switch, and the first end of which is connected with the second output end of the second input circuit, and is used for pulling the voltage of the second output end of the second input circuit according to the voltage of the first output end of the second input circuit under the control of the third switch; And the control end of the eighth feedback unit is connected with the second output end of the second input circuit through a fourth switch, and the first end of the eighth feedback unit is connected with the first output end of the second input circuit and is used for pulling the voltage of the first output end of the second input circuit according to the voltage of the second output end of the second input circuit under the control of the fourth switch.
19. 19. The decision feedback equalizer circuit of claim 18, wherein: The fifth feedback unit comprises a fifth feedback transistor, a first feedback unit and a second feedback unit, wherein the control end of the fifth feedback transistor is the control end of the fifth feedback unit, and the second end of the fifth feedback transistor is the first end of the fifth feedback unit; The sixth feedback unit comprises a sixth feedback transistor, wherein the control end of the sixth feedback transistor is the control end of the sixth feedback unit, and the second end of the sixth feedback transistor is the first end of the sixth feedback unit; the seventh feedback unit comprises a seventh feedback transistor, wherein the control end of the seventh feedback transistor is the control end of the seventh feedback unit, and the first end of the seventh feedback transistor is the first end of the seventh feedback unit; The eighth feedback unit comprises an eighth feedback transistor, wherein the control end of the eighth feedback transistor is the control end of the eighth feedback unit, and the first end of the eighth feedback transistor is the first end of the eighth feedback unit.
20. 20. The decision feedback equalizer circuit of claim 18, wherein: the first switch comprises a first transmission gate, and the first transmission gate is controlled by a first enabling signal; the second switch comprises a second transmission gate, and the second transmission gate is controlled by a second enabling signal; the third switch comprises a third transmission gate, and the third transmission gate is controlled by a third enabling signal; the fourth switch comprises a fourth transmission gate, and the fourth transmission gate is controlled by a fourth enabling signal; the first to fourth enable signals are generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal.

Description

Comparator and decision feedback equalization circuit Technical Field The present application relates to integrated circuits, and more particularly, to a comparator and a decision feedback equalizer circuit. Background Today, the demands of mobile devices such as mobile phones, tablet computers and various wearable accessories are greatly increased, which greatly enriches our daily lives and works. However, due to the limited battery life, higher demands are placed on the power consumption of the various components in the mobile device, and dynamic random access memory (Dynamic Random Access Memory, DRAM) is an essential component in the mobile device, so DRAM is also required to achieve lower operating voltages and lower power consumption. The comparator is an important device for realizing the reading and writing of DRAM data, and the existing comparator can not meet the current use requirement. Disclosure of Invention The application provides a comparator and a decision feedback equalization circuit, which aim to improve the response speed and comparison precision of the comparator, reduce the power consumption of the comparator, enlarge the amplitude range of a reference signal of the comparator, and provide a decision feedback equalization circuit capable of eliminating intersymbol interference, thereby improving the accuracy of a circuit output result. In a first aspect, the present application provides a comparator provided with four inputs and two outputs, comprising: The first input circuit is provided with two geminate transistors, the types of the two geminate transistors are different, the control ends of the two geminate transistors are used as the input ends of the comparator, the two geminate transistors are used for receiving a first input signal and a first reference signal, and the first input circuit is also used for generating a first differential signal according to the first input signal and the first reference signal in a sampling stage; the first positive feedback circuit is connected with the output end of the first input circuit and is used for accelerating the difference value between the first differential signals; The second input circuit is provided with two geminate transistors, the types of the two geminate transistors are different, the control ends of the two geminate transistors are used as the input ends of the comparator, the two geminate transistors are used for receiving a second input signal and a second reference signal, and the second input circuit is also used for generating a second differential signal according to the second input signal and the second reference signal in a sampling stage; The second positive feedback circuit is connected with the output end of the second input circuit and is used for accelerating the difference value between the second differential signals; And the output circuit is provided with an input end and an output end, the output end is the output end of the comparator, and the input end of the output circuit is connected with the output end of the first input circuit and is used for amplifying and latching the voltage signal of the output end of the first input circuit and the voltage signal of the output end of the second input circuit in the regeneration stage so as to output a comparison result. The application provides a decision feedback equalization circuit, which is characterized by comprising four comparators related to the first aspect and the alternative scheme, wherein the comparators are sequentially marked as a first comparator, a second comparator, a third comparator and a fourth comparator; the first input end of the first comparator is used for receiving a first input signal, the second input end of the first comparator is used for receiving a first reference signal, the third input end of the first comparator is connected with the first output end of the fourth comparator, and the fourth input end of the first comparator is connected with the second output end of the fourth comparator; the first input end of the second comparator is used for receiving a first input signal, the second input end of the second comparator is used for receiving a first reference signal, the third input end of the second comparator is connected with the first output end of the first comparator, and the fourth input end of the second comparator is connected with the second output end of the first comparator; The first input end of the third comparator is used for receiving a first input signal, the second input end of the third comparator is used for receiving a first reference signal, the third input end of the third comparator is connected with the first output end of the second comparator, and the fourth input end of the third comparator is connected with the second output end of the second comparator; and the fourth comparator is provided with a first input end for receiving the first input signal, a second input end for receiving the fir