CN-115425929-B - Current multiplexing phase-shifting mixer with high harmonic suppression ratio

CN115425929BCN 115425929 BCN115425929 BCN 115425929BCN-115425929-B

Abstract

The invention discloses a current multiplexing phase-shifting mixer with a high harmonic rejection ratio, which is characterized in that a radio frequency input signal RF IN passes through an orthogonal generation unit to generate I, Q two groups of differential signals, the I, Q two groups of differential signals respectively enter an I-path high harmonic rejection ratio phase-shifting mixing unit and a Q-path high harmonic rejection ratio phase-shifting mixing unit, the I, Q groups of differential signals are mixed with differential local oscillator signals in local oscillator signals and control signals of a time sequence control unit and realize phase shifting to generate I, Q two paths of differential intermediate frequency signals, a positive end of the I-path differential intermediate frequency signals and a positive end of the Q-path differential intermediate frequency signals are input into the same load to generate intermediate frequency positive output signals, a negative end of the I-path differential intermediate frequency signals and a negative end of the Q-path differential intermediate frequency signals are input into the same load to generate intermediate frequency negative output signals, and the intermediate frequency positive output signals and the intermediate frequency negative output signals jointly form intermediate frequency differential output signals. The phase shifting device has a simple and compact structure, improves the phase shifting precision of the system, can realize frequency mixing, and reduces the power consumption of the system.

Inventors

HUANG TONGDE
CAO HANZHANG
HU CHUN
WU WEN

Assignees

南京理工大学

Dates

Publication Date: 20260505
Application Date: 20220905

Claims (7)

1. The current multiplexing phase-shifting mixer with the high harmonic rejection ratio is characterized by comprising an orthogonal generation unit, an I-path high harmonic rejection ratio phase-shifting mixing unit, a Q-path high harmonic rejection ratio phase-shifting mixing unit and a time sequence control unit, wherein a radio frequency signal RF IN is connected with the input end of the orthogonal generation unit, four outputs IRF+, IRF-, QRF+, QRF-, are generated by the orthogonal generation unit, the IRF+, IRF-is connected with the radio frequency signal input end of the I-path high harmonic rejection ratio phase-shifting mixing unit, and the QRF+, QRF-is connected with the radio frequency signal input end of the Q-path high harmonic rejection ratio phase-shifting mixing unit; the externally input local oscillation differential quadrature signals are ILO+, ILO-, QLO+ and QLO-, wherein ILO+ and ILO-are connected with the local oscillation signal input end of the I-path high harmonic rejection ratio phase-shifting mixing unit, QLO+ and QLO-are connected with the local oscillation signal input end of the Q-path high harmonic rejection ratio phase-shifting mixing unit, the I-path high harmonic rejection ratio phase-shifting mixing unit and the Q-path high harmonic rejection ratio phase-shifting mixing unit are respectively provided with two output ends to generate IIF+ and IIF-and QIF+ signals, the IIF+ and QIF+ signals are connected with the same load to realize vector synthesis, the IIF-and QIF-are connected with the same load to realize vector synthesis, and finally a pair of differential output signals of IF+ and IF-are generated; The radio frequency input signal RF IN generates I, Q differential signals through the quadrature generation unit, the I differential signals enter the I high harmonic rejection ratio phase-shifting mixing unit, are mixed with the I differential local oscillation signals in the local oscillation signals and the control signals of the time sequence control unit and realize phase shifting to generate I differential intermediate frequency signals, the Q differential signals enter the Q high harmonic rejection ratio phase-shifting mixing unit, are mixed with the Q differential local oscillation signals in the local oscillation signals and the control signals of the time sequence control unit and realize phase shifting to generate Q differential intermediate frequency signals, the positive end of the I differential intermediate frequency signals and the positive end of the Q differential intermediate frequency signals are input into the same load to generate intermediate frequency positive output signals, and the negative end of the I differential intermediate frequency signals and the negative end of the Q differential intermediate frequency signals are input into the same load to generate intermediate frequency negative output signals; Wherein: The timing control unit comprises an FPGA, wherein control signals output by the FPGA comprise IVbit1, IVbit2, IVbit3, IVbit4, IVbit5, IVbit6, QVbit1, QVbit2, QVbit3, QVbit4, QVbit5 and QVbit6 which are timing control signals and have the period of T p , the IVbit-IVbit 6 control the I-path high-harmonic-rejection-ratio phase-shifting mixing unit to realize the phase control function of the I-path high-harmonic-rejection-ratio phase-shifting mixing unit, and the QVbit-QVbit control the Q-path high-harmonic-rejection-ratio phase-shifting mixing unit to realize the phase control function of the Q-path high-harmonic-rejection-ratio phase-shifting mixing unit; The I-path high-harmonic suppression ratio phase-shifting mixing unit consists of an NMOS tube M 1 , an NMOS tube M 2 , an NMOS tube M 3 , an NMOS tube M 4 , NMOS tube M 5 , NMOS tube M 6 , NMOS tube M 7 , NMOS tube M 8 , NMOS tube M 9 , NMOS tube M 10 , NMOS tube M 11 , NMOS tube M 12 , NMOS tube M 13 , NMOS tube M 14 , NMOS tube M 15 , NMOS tube M 16 , tail current source I SS1 , tail current source I SS2 and tail current source I SS3 , signal IRF+ output end of quadrature generation unit and NMOS tube M 1 , NMOS tube M 4 , NMOS tube M 5 , NMOS tube M 8 , NMOS tube M 9 , The grid electrode of the NMOS tube M 12 is connected, the signal IRF-output end of the quadrature generation unit is connected with the NMOS tube M 2 , the NMOS tube M 3 , the NMOS tube M 6 , The gates of the NMOS tube M 7 , the NMOS tube M 10 and the NMOS tube M 11 are connected, the NMOS tube M 1 , The drains of the NMOS tube M 2 , the NMOS tube M 3 and the NMOS tube M 4 are connected with a tail current source I SS1 , the NMOS tube M 5 , the drains of the NMOS tube M 6 , the NMOS tube M 7 and the NMOS tube M 8 are connected with a tail current source I SS2 , the NMOS tube M 9 , The drains of the NMOS tube M 10 , the NMOS tube M 11 and the NMOS tube M 12 are connected with a tail current source I SS3 , the NMOS tube M 1 , The body end of the NMOS tube M 2 is connected with a control bit IVbit1 generated by the time sequence control unit, the body ends of the NMOS tube M 3 and the NMOS tube M 4 are connected with a control bit IVbit2 generated by the time sequence control unit, the NMOS tube M 5 , The body end of the NMOS tube M 6 is connected with a control bit IVbit generated by the time sequence control unit, the body ends of the NMOS tube M 7 and the NMOS tube M 8 are connected with a control bit IVbit4 generated by the time sequence control unit, the NMOS tube M 9 , The body end of the NMOS tube M 10 is connected with a control bit IVbit generated by the time sequence control unit, the body ends of the NMOS tube M 11 and the NMOS tube M 12 are connected with a control bit IVbit6 generated by the time sequence control unit, the NMOS tube M 1 , NMOS tube M 3 , NMOS tube M 5 , NMOS tube M 7 , NMOS tube M 9 , The drain electrode of the NMOS tube M 11 is connected with the source electrodes of the NMOS tube M 13 and the NMOS tube M 14 , the NMOS tube M 2 , NMOS tube M 4 , NMOS tube M 6 , NMOS tube M 8 , NMOS tube M 10 , The drain electrode of the NMOS tube M 12 is connected with the source electrodes of the NMOS tube M 15 and the NMOS tube M 16 , ILO+ in the externally input local oscillation signal is connected with the NMOS tube M 13 , The grid electrode of the NMOS tube M 16 is connected, the local oscillation signal ILO-is connected with the grid electrodes of the NMOS tube M 14 and the NMOS tube M 15 , the NMOS tube M 13 , NMOS tube M 14 , NMOS tube M 15 , The body end of the NMOS tube M 16 is connected with the ground, the NMOS tube M 13 is connected with the drain electrode of the NMOS tube M 15 , and the NMOS tube M 14 is connected with the drain electrode of the NMOS tube M 16 ; The Q-path high-harmonic suppression ratio phase-shifting mixing unit consists of an NMOS tube M 17 , an NMOS tube M 18 , an NMOS tube M 19 , an NMOS tube M 20 , NMOS tube M 21 , NMOS tube M 22 , NMOS tube M 23 , NMOS tube M 24 , NMOS tube M 25 , NMOS tube M 26 , NMOS tube M 27 , NMOS tube M 28 , NMOS tube M 29 , NMOS tube M 30 , NMOS tube M 31 , NMOS tube M 32 , Tail current source I SS4 , tail current source I SS5 and tail current source I SS6 , signal QRF+ output end of quadrature generation unit and NMOS tube M 17 , NMOS tube M 20 , NMOS tube M 21 , NMOS tube M 24 , NMOS tube M 25 , The grid electrode of the NMOS tube M 28 is connected, the signal QRF-output end of the quadrature generation unit is connected with the NMOS tube M 18 , the NMOS tube M 19 , the NMOS tube M 22 , The gates of the NMOS tube M 23 , the NMOS tube M 26 and the NMOS tube M 27 are connected, the NMOS tube M 17 , The drains of the NMOS tube M 18 , the NMOS tube M 19 and the NMOS tube M 20 are connected with a tail current source I SS4 , the NMOS tube M 21 , The drains of the NMOS tube M 22 , the NMOS tube M 23 and the NMOS tube M 24 are connected with a tail current source I SS5 , the NMOS tube M 25 , The drains of the NMOS tube M 26 , the NMOS tube M 27 and the NMOS tube M 28 are connected with a tail current source I SS6 , the NMOS tube M 17 , the body end of the NMOS tube M 18 is connected with a control bit QVbit1 generated by the time sequence control unit, the body ends of the NMOS tube M 19 and the NMOS tube M 20 are connected with a control bit QVbit2 generated by the time sequence control unit, the NMOS tube M 21 , The body end of the NMOS tube M 22 is connected with a control bit QVbit generated by the time sequence control unit, the body ends of the NMOS tube M 23 and the NMOS tube M 24 are connected with a control bit QVbit4 generated by the time sequence control unit, the NMOS tube M 25 , The body end of the NMOS tube M 26 is connected with a control bit QVbit generated by the time sequence control unit, the body ends of the NMOS tube M 27 and the NMOS tube M 28 are connected with a control bit QVbit6 generated by the time sequence control unit, the NMOS tube M 17 , NMOS tube M 19 , NMOS tube M 21 , NMOS tube M 23 , NMOS tube M 25 , The drain electrode of the NMOS tube M 27 is connected with the source electrodes of the NMOS tube M 29 and the NMOS tube M 30 , the NMOS tube M 17 , NMOS tube M 20 , NMOS tube M 22 , NMOS tube M 24 , NMOS tube M 26 , The drain electrode of the NMOS tube M 28 is connected with the source electrodes of the NMOS tube M 31 and the NMOS tube M 32 , and the externally input local oscillation signal QLO+ and the NMOS tube M 29 , The grid electrode of the NMOS tube M 32 is connected, the local oscillation signal QLO-input end is connected with the grid electrodes of the NMOS tube M 30 and the NMOS tube M 31 , the NMOS tube M 29 , NMOS tube M 30 , NMOS tube M 31 , the body end of the NMOS tube M 32 is connected with the ground, the NMOS tube M 29 is connected with the drain electrode of the NMOS tube M 31 , and the NMOS tube M 30 is connected with the drain electrode of the NMOS tube M 32 .
2. The current multiplexing phase shifting mixer with high harmonic rejection ratio according to claim 1, wherein the quadrature generating unit is composed of an input balun and an all-pass quadrature filter, wherein an input radio frequency signal is connected with one input end of the input balun, differential input radio frequency signals rf+ and RF-are generated after the input balun, and then the differential input radio frequency signals rf+ and RF-are respectively connected with two input ends of the quadrature all-pass filter, and input radio frequency quadrature differential signals irf+, IRF-, QRF-are generated after the input balun.
3. The current multiplexing phase-shifting mixer with high harmonic rejection ratio according to claim 1, wherein the NMOS tube M 13 in the I-channel high harmonic rejection ratio phase-shifting mixer is connected to the drain of the NMOS tube M 15 , then connected to the drain of the NMOS tube M 31 and the NMOS tube M 29 in the Q-channel high harmonic rejection ratio phase-shifting mixer, and then connected to a load, thereby completing vector synthesis of current form, and obtaining an intermediate frequency output positive signal IF +, and the NMOS tube M 14 in the I-channel high harmonic rejection ratio phase-shifting mixer is connected to the drain of the NMOS tube M 16 , then connected to the drain of the NMOS tube M 30 and the NMOS tube M 32 in the Q-channel high harmonic rejection ratio phase-shifting mixer, and then connected to the load, thereby completing vector synthesis of current form, and finally obtaining an intermediate frequency output negative signal IF of differential output form.
4. The current-multiplexing phase-shifting mixer with high harmonic rejection ratio according to claim 1, wherein the timing control logic is IVbit to 1 in a relative cycle From time 0 to time 0 of (2) Is at high level and the rest of time is at low level, IVbit is at a relative period From time 0 to time 0 of (2) At low level and high level at other times, IVbit in a relative period Is the first of (2) From moment to moment Is high and the rest of the time is low, IVbit is in a relative period Is the first of (2) From moment to moment At low level and high level at other times, IVbit in a relative period Is the first of (2) From moment to moment At a high level and the rest at a low level, IVbit in a relative period Is the first of (2) From moment to moment At low level and high level at other times, QVbit a relative period Is the first of (2) From moment to moment Is at high level and the rest of time is at low level, QVbit is at a relative period Is the first of (2) From moment to moment At low level and high level at other times, QVbit in a relative period Is the first of (2) From moment to moment Is high and the rest of the time is low, QVbit is in a relative period A kind of electronic device From moment to moment At low level and high level at other times, QVbit in a relative period Is the first of (2) From moment to moment At a high level and the rest at a low level, IVbit in a relative period Is the first of (2) From moment to moment At a low level and the rest of the time is at a high level.
5. A current-multiplexing phase-shifting mixer with high harmonic rejection ratio according to claim 1 or 3, wherein the current amplitude ratio of the tail current source I SS1 , the tail current source I SS2 , and the tail current source I SS3 in the I-path high harmonic rejection ratio phase-shifting mixer unit is 1: The current amplitude ratio of a tail current source I SS4 , a tail current source I SS5 and a tail current source I SS6 in the 1;Q-path high-harmonic suppression ratio phase-shifting mixing unit is 1: 1, and the current amplitude of the tail current source I SS1 is equal to the current amplitude of the tail current source I SS4 .
6. The current-multiplexing phase-shifting mixer with high harmonic rejection ratio according to claim 4, wherein the phase-shifting function of the current-multiplexing phase-shifting mixer adjusts a pulse start time point of the control signal outputted from the FPGA To achieve that if the beam is directed at an angle of The relationship with the pulse start time point is: The phase change of the current multiplexing phase-shifting mixer with the high harmonic rejection ratio at 0-2 pi is realized by adjusting the pulse starting time.
7. The current multiplexing phase-shifting mixer with high harmonic rejection ratio according to claim 1, wherein the mixing function of the phase-shifting mixer mixes the input radio frequency differential quadrature signals irf+, IRF-, qrf+, QRF-generated by the quadrature generation unit through the I-path high harmonic rejection ratio phase-shifting mixing unit and the Q-path high harmonic rejection ratio phase-shifting mixing unit respectively by the differential quadrature local oscillator signals ilo+, ILO-, qlo+, QLO-input externally, and finally achieves the effect of mixing the radio frequency input signals to the intermediate frequency differential output signals.

Description

Current multiplexing phase-shifting mixer with high harmonic suppression ratio Technical Field The invention relates to a microwave monolithic integrated circuit and a microelectronic technology, in particular to a current multiplexing phase-shifting mixer with a high harmonic suppression ratio. Background With the rapid development of wireless communication systems, phased array systems are widely used in various fields, including aerospace, proximity detection, precision guidance, etc. The phase shifter and the mixer are core modules in the phased array system, and the phase shifter realizes the beam scanning function of the phased array system by controlling the phase of a received signal or a transmitted signal of each unit in the antenna array. For a conventional active phase shifter, a vector synthesis phase shifting architecture is generally adopted, the phase shifting precision depends on control bits and a phase shifting range, but with the continuous increase of working frequency, the phase shifting precision cannot be further improved by a method for improving the control bits, a more complex calibration circuit is required, and more power consumption is consumed. Whereas for a mixer it takes on the function of mixing up an intermediate frequency signal on the transmit path to a radio frequency signal or mixing down a radio frequency signal on the receive path to an intermediate frequency signal. The mixer has indexes such as conversion gain, noise coefficient, linearity and power consumption, but in a conventional phased array architecture, two discrete architectures are generally adopted in the architecture design of the phase shifter and the mixer, so that the overall power consumption is higher, the service life of the overall system is not facilitated, and meanwhile, the concept of green and environment protection in the development at present is also not facilitated. Disclosure of Invention The invention aims to provide a current multiplexing phase-shifting mixer with a high harmonic rejection ratio so as to solve the problem of lower phase-shifting precision in the traditional phase-shifting architecture. The technical scheme for realizing the purpose of the invention is that the current multiplexing phase-shifting mixer with the high harmonic suppression ratio comprises a quadrature generation unit, an I-path high harmonic suppression ratio phase-shifting mixing unit, a Q-path high harmonic suppression ratio phase-shifting mixing unit and a time sequence control unit. The input radio frequency signal RF IN is connected with the input end of the quadrature generation unit, the quadrature generation unit generates four input radio frequency quadrature differential signals IRF+, IRF-, QRF+ and QRF-, wherein IRF+ and IRF-are connected with the radio frequency signal input end of the I path high harmonic rejection ratio phase-shifting mixing unit, QRF+ and QRF-are connected with the radio frequency signal input end of the Q path high harmonic rejection ratio phase-shifting mixing unit, the externally input local oscillation differential quadrature signals are ILO+, ILO-, QLO+ and QLO-, wherein ILO+ and ILO-are connected with the local oscillation signal input end of the I path high harmonic rejection ratio phase-shifting mixing unit, QLO+, QLO-and Q path high harmonic rejection ratio phase-shifting mixing unit are respectively provided with two output ends, I path intermediate frequency differential output signals IIF+ and IIF-and QF-are generated, the IIF+ and QIF+ are connected with the same load to realize vector synthesis, the IIF-, QIF-and QF-are connected with the same load to finally realize vector synthesis to generate a pair of differential signals and IF-and differential signals; The radio frequency input signal RF IN generates I, Q differential signals through the quadrature generation unit, the I differential radio frequency signals enter the I high harmonic rejection ratio phase shift mixing unit and are mixed with the I differential local oscillation signals in the local oscillation signals and the control signals of the time sequence control unit to realize phase shift to generate I differential intermediate frequency signals, the Q differential radio frequency signals enter the Q high harmonic rejection ratio phase shift mixing unit and are mixed with the Q differential local oscillation signals in the local oscillation signals and the control signals of the time sequence control unit to realize phase shift to generate Q differential intermediate frequency signals, the positive end of the I differential intermediate frequency signals and the positive end of the Q differential intermediate frequency signals are input into the same load to generate the positive end output of the intermediate frequency signals, the negative end of the I differential intermediate frequency signals and the negative end of the Q differential intermediate frequency signals are input into the same load