CN-115425990-B - Verification method and device suitable for LDPC decoder and decoder

CN115425990BCN 115425990 BCN115425990 BCN 115425990BCN-115425990-B

Abstract

The invention provides a checking method and device suitable for an LDPC decoder and the decoder, wherein the method comprises the steps of storing a judgment result generated by iterative updating as an N-th judgment result when the N-th iterative updating is performed, comparing and checking the N-th judgment result with the N-1-th judgment result to obtain an N-th checking result, judging the N-th checking result to be the same or different, jumping to the next step if the N-th checking result is the same or the N reaches the maximum iterative times, otherwise continuing the next checking, and outputting the decoding result. By comparing the decoding result of the current iteration with the decoding result of the last iteration, the traditional mode of checking by using a check matrix is replaced by H.c T =0, and the complexity of the implementation of the hardware circuit is reduced.

Inventors

SUN QIAN

Assignees

江苏屹信航天科技股份有限公司
江苏屹信航天科技有限公司

Dates

Publication Date: 20260421
Application Date: 20220901
Priority Date: 20220901

Claims (9)

1. A method of verification for an LDPC decoder, comprising the steps of: S301, storing a judgment result generated by iterative updating as an Nth judgment result when the Nth iterative updating is performed, wherein N is a positive integer greater than or equal to 1; S302, comparing and checking the Nth judgment result with the N-1 th judgment result to obtain an Nth check result, wherein the Nth check result is the same or different; comparing and checking the N th decision bit newly generated at each moment with the N-1 th decision bit at the corresponding moment, stopping the comparison and checking when the comparison and checking results are different, and confirming that the N th checking results are different; S303, judging the Nth verification result, if the Nth verification result is the same or the N reaches the maximum iteration number, jumping to the step S304, otherwise, ending the verification; S304, outputting a decoding result.
2. The method for checking an LDPC decoder according to claim 1, wherein the step S301 further comprises: Uniformly dividing a check matrix of the LDPC code into 14 blocks according to rows and 112 blocks according to columns, so that a sub-cyclic matrix with the size of 511 multiplied by 511 is divided into 7 minimum sub-matrices with the size of 73 multiplied by 73, and simultaneously carrying out iterative updating on each minimum sub-matrix when each iterative updating is carried out; determining the bit number of a group of decision bits generated in real time at the same time as 98; 98 decision bit registers with the length of 73 bits are correspondingly arranged and used for storing the decision bits.
3. The method for checking an LDPC decoder according to claim 2, wherein the step S301 further comprises: storing the decision bits generated at different moments into the decision bit register according to the sequence from low to high; when the set of decision bits is stored, bit data in each decision bit register is shifted one bit to the left, then each decision bit is stored in a 0 th bit of one decision bit register correspondingly, each decision bit register stores one decision bit, and the 0 th bit is the lowest bit.
4. The method for checking an LDPC decoder according to claim 3, wherein the step S302 further comprises: When the set of decision bits is stored, the highest decision bit in the decision bit register is shifted out and forms another set of decision bits, the two sets of decision bits are compared and checked, and the comparison results are recorded, wherein the comparison results are the same or different.
5. The method for LDPC decoder according to claim 4, wherein the step S302 further comprises: And when comparison and verification are carried out, the 98 judgment bits generated in the current iteration are subjected to bit splicing to obtain a current judgment comparison signal, the highest judgment bit before the left shift of the judgment bit register is subjected to bit splicing to obtain a last judgment comparison signal, and then the current judgment comparison signal is compared with the last judgment comparison signal to obtain a comparison result.
6. The method according to claim 5, wherein the step S302 further comprises: When the set of decision bits is stored, the comparison result of the last set of decision bits is read and judged, when the comparison results are the same, continuing to compare; and when the comparison results are different, the comparison is not performed again.
7. The method according to claim 6, wherein the step S304 further comprises: the decoding result is obtained by splicing the judgment result generated by the iterative updating.
8. The verification device suitable for the LDPC decoder is characterized by comprising a receiving unit, a storage unit, a comparison unit and a control unit; The receiving unit receives a judgment result generated by iterative updating in the LDPC decoder and stores the judgment result into the storage unit; The storage unit stores decision bits in the decision results generated at different moments into a register according to the sequence from low to high, and shifts the register one bit left when new bits are stored each time, so that the register is recycled; the control unit judges when to start comparison and stop comparison and outputs decoding results generated by iterative updating in the LDPC decoder; The comparison unit receives the instruction of the control unit, reads the judgment bits of the storage unit and performs comparison verification; The verification method of the verification device comprises the steps of S301, when iteration updating is carried out for the nth time, a judgment result generated by the iteration updating is stored as an nth judgment result, N is a positive integer which is larger than or equal to 1, S302, comparison and verification are carried out on the nth judgment result and the nth-1 judgment result to obtain an nth verification result, the nth verification result is identical or different, the nth judgment result comprises a plurality of nth judgment bits which are generated in real time at different moments, comparison and verification are carried out on the nth judgment bit which is newly generated at each moment and the nth-1 judgment bit at the corresponding moment, when the comparison and verification result is different, comparison and verification are stopped, and the nth verification result is confirmed to be different, S303, judgment is carried out on the nth verification result, if the nth verification result is identical or the nth verification result reaches the maximum iteration time, S304 is carried out, otherwise, decoding results are output.
9. An LDPC decoder comprising the verification apparatus of claim 8 adapted for use in an LDPC decoder.

Description

Verification method and device suitable for LDPC decoder and decoder Technical Field The invention belongs to the field of communication, and particularly relates to a verification method and device suitable for an LDPC decoder and the decoder. Background LDPC codes, low DENSITY PARITY CHECK codes, were first proposed by Gallager doctor in 1962 and rediscovered by Mackey and Neal in 1996. The LDPC code has excellent error correction performance and lower hardware implementation complexity, so that the LDPC code is widely applied to the field of deep space communication. With the advancement of technology, various decoding algorithms are proposed by the academia for LDPC. The probability domain BP decoding algorithm is one of decoding algorithms of the main stream of LDPC codes, but the algorithm needs a large number of multiplication operations and is difficult to realize through a hardware circuit. The logarithmic domain LLR (Log LIKELY RATE) BP decoding algorithm changes multiplication operation in the probability domain BP decoding algorithm into addition operation, so that the operation complexity is reduced, but the hardware circuit implementation complexity is still high due to logarithmic operation. The minimum sum decoding algorithm (MSA) is a further simplification of the logarithmic domain LLR BP decoding algorithm, and the simplified MSA only needs addition and comparison operations. The multiplicative modified minimum sum decoding algorithm (NMSA) is a correction to the MSA to further approximate its error correction performance to the logarithmic domain LLR BP decoding algorithm. NMSA, although having low computational complexity, is extremely suitable for hardware circuit implementation, because of its decoding mechanism based on two-phase information Transfer (TPMP), there is much invalid waiting time. With the development of communication technology, requirements are further put on decoding speed and efficiency, and how to design a corresponding FPGA-based decoder to perform LDPC decoding and obtain parallel high-speed decoding efficiency is a problem faced by those skilled in the art. Disclosure of Invention The technical problem to be solved by the invention is to provide a verification method suitable for LDPC decoder, which has lower operation complexity and is easier to realize by hardware circuit. In order to solve the technical problems, the invention adopts the following technical scheme: in one aspect, the present invention provides a verification method for an LDPC decoder, comprising the steps of: s301, storing a judgment result generated by iterative updating as an Nth judgment result when the Nth iterative updating is performed, wherein N is a positive integer greater than or equal to 1; S302, comparing and checking the Nth judgment result with the N-1 th judgment result to obtain an Nth check result, wherein the Nth check result is the same or different; s303, judging the Nth verification result, if the Nth verification result is the same or N reaches the maximum iteration number, jumping to the step S304, otherwise, ending the verification; S304, outputting a decoding result. Further, step S302 further includes: the Nth decision result comprises a plurality of Nth decision bits generated in real time at different moments; comparing and checking the N th decision bit newly generated at each moment with the N-1 st decision bit at the corresponding moment; and stopping the comparison and verification when the comparison and verification results are different, and confirming that the Nth verification result is different. Further, step S301 further includes: Uniformly dividing a check matrix of the LDPC code into 14 blocks according to rows and 112 blocks according to columns, so that a sub-cyclic matrix with the size of 511 multiplied by 511 is divided into 7 minimum sub-matrices of 73 multiplied by 73, and simultaneously carrying out iterative updating on each minimum sub-matrix when each iterative updating is carried out; determining the bit number of a group of decision bits generated in real time at the same time as 98; 98 decision bit registers of 73 bits in length are correspondingly arranged for storing the decision bits. Further, step S301 further includes: Storing decision bits generated at different moments into a decision bit register according to the sequence from low to high; When a group of judgment bits are stored, bit data in each judgment bit register is shifted one bit to the left, then each judgment bit is stored in the 0 th bit of one judgment bit register correspondingly, each judgment bit register stores one judgment bit, and the 0 th bit is the lowest bit. Further, step S302 further includes: When one group of decision bits is stored, the most significant decision bit in the decision bit register is shifted out and forms another group of decision bits, the two groups of decision bits are compared and checked, and the comparison results are recorded to be the