CN-115437824-B - Cache control method, system and related components

CN115437824BCN 115437824 BCN115437824 BCN 115437824BCN-115437824-B

Abstract

The application discloses a cache control method, a cache control system and related components, which relate to the field of cache, wherein the method comprises the steps of obtaining a request message of a current CPU; the method comprises the steps of responding to a request message according to a current catalog working mode, monitoring the hit rate of the request message, judging whether the hit rate reaches a target hit rate, and if not, adjusting group connection structure parameters in the current catalog working mode to respond to the rest part of the request message according to the adjusted catalog working mode. The application adjusts the group connection structure parameters of the target working mode with the hit rate lower than the target hit rate by monitoring the hit rate of the request message in the response process, thereby realizing the effects of improving the hit rate of the whole request message and reducing the access delay probability with lower cost.

Inventors

DING YUE
GAO YUXIN

Assignees

山东云海国创云计算装备产业创新中心有限公司
山东云海国创云计算装备产业创新中心有限公司

Dates

Publication Date: 20260421
Application Date: 20220830
Priority Date: 20220830

Claims (8)

1. A method of cache control, comprising: Acquiring a request message of a current CPU; Responding to the request message according to the current directory working mode, and monitoring the hit rate of the request message; judging whether the hit rate reaches a target hit rate or not; If not, the group connection structure parameters in the current directory working mode are adjusted to respond to the rest part of the request message according to the adjusted directory working mode, wherein the group connection structure parameters of the directory working mode are adjustable, the address mapping established by the group connection structure is dynamic split address mapping, the directory entry in the access message is determined by using a dynamic split address mapping mode; correspondingly, the method further comprises the steps of: monitoring the hit rate of the request message when the current directory working mode responds to the request message; judging whether the hit rate reaches the target hit rate or not; If not, executing the following actions until the hit rate reaches the target hit rate: Adjusting group connection structure parameters of the current catalog working mode, and responding to the rest part of the request message according to the adjusted catalog working mode; correspondingly, the method further comprises the steps of: If the hit rates corresponding to all the directory operation modes do not reach the target hit rate, selecting the directory operation mode corresponding to the highest hit rate from all the directory operation modes to respond to the rest part of the request message.
2. The cache control method according to claim 1, wherein after the request message of the current CPU is obtained, comprising: determining group connection structure parameters of the current directory working mode according to the type of the request message; The types of the request message comprise a memory continuous read-write type and a memory discontinuous read-write type.
3. The cache control method of claim 1, further comprising: receiving a mode instruction; And adjusting group connection structure parameters in the current catalogue working mode according to the mode instruction so as to respond to the rest part of the request message according to the adjusted catalogue working mode.
4. A cache control method according to any one of claims 1 to 3, wherein said adjusting the set of connection structure parameters in the current directory operation mode to respond to the remainder of the request message according to the adjusted directory operation mode comprises: Setting all cache lines in a cache as invalid state, adjusting group connection structure parameters in the current directory working mode, and enabling and updating data for all the cache lines according to the current directory working mode and the rest part of the request message.
5. The cache control method of claim 4, further comprising: and replacing all the cache lines according to an LRU replacement algorithm corresponding to the set connection structure parameters in the current directory working mode.
6. A cache control system, comprising: The acquisition module is used for acquiring a request message of the current CPU; The response module is used for responding to the request message according to the current directory working mode and monitoring the hit rate of the request message; The judging module is used for judging whether the hit rate reaches a target hit rate or not; The action module is used for adjusting group connection structure parameters in the current catalogue working mode if the result of the judgment module is negative, so as to trigger the response module to respond the rest part of the request message according to the current catalogue working mode; the Index mapping part realizes that the mapping bit width is adjustable, the adjustable space is complementary with the Tag part address bit, and under the variable directory cache configuration mode, the Tag part mapping bit width and the Index part mapping bit width in CACHE LINE are dynamically adjusted to realize that the mapped message can be normally matched under different modes; correspondingly, the method further comprises the steps of: monitoring the hit rate of the request message when the current directory working mode responds to the request message; judging whether the hit rate reaches the target hit rate or not; If not, executing the following actions until the hit rate reaches the target hit rate: Adjusting group connection structure parameters of the current catalog working mode, and responding to the rest part of the request message according to the adjusted catalog working mode; correspondingly, the method further comprises the steps of: If the hit rates corresponding to all the directory operation modes do not reach the target hit rate, selecting the directory operation mode corresponding to the highest hit rate from all the directory operation modes to respond to the rest part of the request message.
7. An electronic device, comprising: a memory for storing a computer program; A processor for implementing the steps of the cache control method according to any one of claims 1 to 5 when executing said computer program.
8. A readable storage medium, characterized in that the readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the cache control method according to any of claims 1 to 5.

Description

Cache control method, system and related components Technical Field The present invention relates to the field of cache, and in particular, to a cache control method, system, and related components. Background A cache buffer cache, referred to as a cache, is a level one memory interposed between a main memory and a CPU (Central Processing Unit ) for providing read and write services to the CPU at a higher speed than the main memory. When CPU reads data, the hardware firstly decodes the column number field of the access address automatically to compare the whole row number of the column in the cache with the row number field of the access main memory address, if the two are the same, the main memory unit to be accessed is in the high-speed memory, which is called hit, the hardware maps the address of the access main memory into the address of the high-speed memory and executes the access operation, if the two are different, which is called miss, the hardware executes the operation of accessing the main memory and automatically transfers the unit into the empty memory unit group in the same column of the high-speed memory, at the same time, the row number of the unit in the main memory is stored in the unit of the corresponding position of the associative memory, and when the miss occurs and the corresponding position of the high-speed memory is not empty, one of the units in the column is eliminated to store the newly transferred unit in the free position, which is called replacement. The cache memory is internally provided with address mapping conversion in the form of a directory, thereby establishing a correspondence between the address of a main memory and the address of the cache memory for certain data. The common address mapping conversion structure comprises a full-connection structure, a direct-connection structure, a group-connection structure and the like, wherein the full-connection structure has higher hit rate, more matching objects, low access speed and more hardware resource consumption, the direct-connection structure has simple circuit design, low hit rate and frequent replacement operation, and the group-connection structure is a scheme between the full-connection structure and the direct-connection structure and has higher hit rate and utilization rate. However, for different upper-layer application programs, the read-write modes of the upper-layer application programs on the memory are different, the hit rates of the caches responding to different read-write commands are different under a constant group connection structure, and when the hit rates are lower, the situation of cache access delay can occur, so that the running speed of the upper-layer application programs is unstable. Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art. Disclosure of Invention Accordingly, the present invention is directed to a cache control method, system and related components with high hit rate. The specific scheme is as follows: a cache control method, comprising: Acquiring a request message of a current CPU; Responding to the request message according to the current directory working mode, and monitoring the hit rate of the request message; judging whether the hit rate reaches a target hit rate or not; If not, the group connection structure parameters in the current catalog working mode are adjusted so as to respond to the rest part of the request message according to the adjusted catalog working mode. Preferably, the cache control method further includes: monitoring the hit rate of the request message when the current directory working mode responds to the request message; judging whether the hit rate reaches the target hit rate or not; If not, executing the following actions until the hit rate reaches the target hit rate: and adjusting group connection structure parameters of the current catalogue working mode, and responding to the rest part of the request message according to the adjusted catalogue working mode. Preferably, the cache control method further includes: If the hit rates corresponding to all the directory operation modes do not reach the target hit rate, selecting the directory operation mode corresponding to the highest hit rate from all the directory operation modes to respond to the rest part of the request message. Preferably, after the obtaining the request message of the current CPU, the method includes: determining group connection structure parameters of the current directory working mode according to the type of the request message; The types of the request message comprise a memory continuous read-write type and a memory discontinuous read-write type. Preferably, the cache control method further includes: receiving a mode instruction; And adjusting group connection structure parameters in the current catalogue working mode according to the mode instruction so as to respond to the rest part of the