CN-115454203-B - Method for correcting phase difference between data and clock, receiver, chip and device

CN115454203BCN 115454203 BCN115454203 BCN 115454203BCN-115454203-B

Abstract

The application relates to a correction method of phase difference between data and clocks, which comprises the steps that a receiver performs secondary synchronization on IO signals based on CLK signals to obtain IO synchronous signals, a start bit falling edge pulse signal is obtained according to the IO synchronous signals, then a start bit enabling signal is set, delay time of the receiver and the IO signals is obtained, when check bit errors of character frames received by the receiver occur, compensation time is determined, a data line is taken over at the compensation time according to the delay time, and the data line is driven to be low level, so that a transmitter retransmits the character frames. The receiver can better receive the start bit on the data line, has smaller time sequence requirement on the other party of communication, and can communicate with more products. The conditions of misjudgment, bidirectional driving and the like possibly occurring to the transmitter are avoided, so that the communication between the two parties can be performed stably, the performance of the interface is improved, and the compatibility is enhanced. The application also relates to a receiver, a chip and a device.

Inventors

ZHANG JIANLONG
LANG XIAOGUANG
WU XIAOTONG
WANG XINLONG

Assignees

北京宏思电子技术有限责任公司

Dates

Publication Date: 20260512
Application Date: 20220914

Claims (12)

1. A method for correcting a phase difference between data and a clock, the method comprising: The receiver performs secondary synchronization on the IO signal based on the CLK signal to obtain an IO synchronization signal; Obtaining a start bit falling edge pulse signal according to the IO synchronous signal; The hardware logic unit of the receiver sets a start bit enabling signal according to the start bit falling edge pulse signal; acquiring the synchronous delay between the IO synchronous signal and the initial bit falling edge of the IO signal, calculating the logic delay between the IO synchronous signal and the initial bit enabling signal, and obtaining the delay time of the receiver and the IO signal according to the synchronous delay and the logic delay; The receiver judges whether check bits of the character frame are wrong; if yes, the receiver determines a compensation time for taking over the data line according to the first preset time and the delay time, takes over the data line at the compensation time, and drives the data line to be low level so that the transmitter resends the character frame.
2. The method according to claim 1, wherein the receiver determines the compensation time for taking over the data line according to a first preset time and the delay time, specifically comprising: The receiver advances the first preset time of the receiver by the delay time length to obtain a compensation time when the receiver takes over the data line, so that the position of the compensation time corresponding to the CLK signal coincides with the position of the first preset time of the IO signal corresponding to the CLK signal.
3. The method according to claim 1, wherein said driving the data line low causes the transmitter to retransmit the character frame, comprising: And driving the data line to be at a low level so that the transmitter detects at a second preset time and retransmits the character frame at a third preset time.
4. The method of claim 1, wherein the obtaining a start bit falling edge pulse signal according to the IO synchronization signal specifically comprises: And after inverting the IO synchronous signal, performing AND operation on the IO synchronous signal and a sampling signal obtained by sampling the IO synchronous signal to obtain the initial bit falling edge pulse signal.
5. The method according to claim 1, wherein the hardware logic of the receiver sets a start bit enable signal according to the start bit falling edge pulse signal, specifically comprising: And when the start bit falling edge pulse signal is 1, setting the start bit enabling signal to be 1.
6. The method of claim 1, wherein after the receiver takes over the data line, further comprising: the hardware logic unit of the receiver sets the output enable signal to a high level and sets the value of the output data signal to a first preset value.
7. The method of claim 6, wherein the receiver driving the data line low, comprises: when the output enabling signal is at a high level, the receiver controls the data line, and a pin of the receiver outputs a first voltage according to the value of the output data signal to drive the data line to a low level.
8. A method according to claim 1 or 2, characterized in that the first preset moment is the 10.5 th moment of a character frame.
9. A method according to claim 3, wherein the second preset time is the 11 th time of a character frame and the third preset time is the 13 th time of a character frame.
10. A receiver, wherein the receiver comprises a first processing unit, a second processing unit, a third processing unit, a fourth processing unit and a fifth processing unit; The first processing unit is used for carrying out secondary synchronization on the IO signals based on the CLK signals to obtain IO synchronous signals; the second processing unit is used for obtaining a start bit falling edge pulse signal according to the IO synchronous signal; The third processing unit is used for setting a start bit enabling signal by a hardware logic unit of the receiver according to the start bit falling edge pulse signal; The fourth processing unit is configured to obtain a synchronization delay between the IO synchronization signal and a start bit falling edge of the IO signal, calculate a logic delay between the IO synchronization signal and the start bit enabling signal, and obtain a delay duration of the receiver and the IO signal according to the synchronization delay and the logic delay; the fifth processing unit is used for judging whether check bits of the character frame are wrong or not; if yes, the receiver determines a compensation time for taking over the data line according to the first preset time and the delay time, takes over the data line at the compensation time, and drives the data line to be low level so that the transmitter resends the character frame.
11. A chip configured as a receiver, characterized in that the receiver performs the method of correcting for phase differences between data and clocks according to any one of claims 1-9.
12. An electronic device comprising a receiver that performs the method of correcting for phase differences between data and clocks of any one of claims 1-9.

Description

Method for correcting phase difference between data and clock, receiver, chip and device Technical Field The present application relates to the field of computer technologies, and in particular, to a method, a receiver, a chip, and an apparatus for correcting a phase difference between data and clocks. Background The smart card and the card reader system thereof are widely applied to the fields of mobile communication, financial payment, transportation trip, public utilities and the like. In general, the contact smart card and its information exchange with the card reader are standard in ISO7816 protocol, including PSAM card, SAM card, SIM card, etc., all conform to ISO7816 protocol. In the conventional design, when an interface taking the ISO7816 protocol as a standard is taken as a receiver, the received data and the clock line are generally considered to be synchronous, but due to different logic paths inside a chip, loss of actual transmission, non-standardization of the interface and the like, the phase difference exists between the data received by the receiver and the clock line, and when the phase difference is large, the receiver cannot correctly receive the start bit on the data line, so that normal communication between the interfaces cannot be realized at all, and the communication compatibility of the interface taking the ISO7816 protocol as the standard in the conventional design is poor. Disclosure of Invention The embodiment of the application provides a method for correcting phase difference between data and clocks, a receiver, a chip and equipment. The technical scheme is as follows: in a first aspect, an embodiment of the present application provides a method for correcting a phase difference between data and a clock, including: The receiver performs secondary synchronization on the IO signal based on the CLK signal to obtain an IO synchronization signal; Obtaining a start bit falling edge pulse signal according to the IO synchronous signal; The hardware logic unit of the receiver sets a start bit enabling signal according to the start bit falling edge pulse signal; Acquiring the synchronous delay between the IO synchronous signal and the initial bit falling edge of the IO signal, calculating the logic delay between the IO synchronous signal and the initial bit enabling signal, and obtaining the delay time of the receiver and the IO signal according to the synchronous delay and the logic delay; the receiver judges whether check bits of the character frame are wrong; If yes, the receiver determines a compensation time for taking over the data line according to a first preset time and the time delay time, takes over the data line at the compensation time, drives the data line to be low level, and enables the transmitter to resend the character frame. In a second aspect, an embodiment of the present application provides a receiver, where the receiver includes a first processing unit, a second processing unit, a third processing unit, a fourth processing unit, and a fifth processing unit; The first processing unit is used for carrying out secondary synchronization on the IO signals based on the CLK signals to obtain IO synchronous signals; the second processing unit is used for obtaining a start bit falling edge pulse signal according to the IO synchronous signal; The third processing unit is used for setting a start bit enabling signal by a hardware logic unit of the receiver according to the start bit falling edge pulse signal; The fourth processing unit is configured to obtain a synchronization delay between the IO synchronization signal and a start bit falling edge of the IO signal, calculate a logic delay between the IO synchronization signal and the start bit enable signal, and obtain delay durations of the receiver and the IO signal according to the synchronization delay and the logic delay; the fifth processing unit is used for judging whether check bits of the character frame are wrong or not; If yes, the receiver determines a compensation time for taking over the data line according to a first preset time and the time delay time, takes over the data line at the compensation time, drives the data line to be low level, and enables the transmitter to resend the character frame. In a third aspect, an embodiment of the present application provides a chip configured as a receiver, where the receiver performs the method for correcting a phase difference between data and clocks according to the first aspect. In a fourth aspect, an embodiment of the present application provides an apparatus, where the apparatus includes a receiver, and the receiver performs the method for correcting a phase difference between data and clocks according to the first aspect. The technical scheme provided by the embodiments of the application has the beneficial effects that at least: According to the method for correcting the phase difference between the data and the clock, which is provided by the embodiment of