CN-115483288-B - MOSFET structure, manufacturing method, power device and electronic equipment

CN115483288BCN 115483288 BCN115483288 BCN 115483288BCN-115483288-B

Abstract

A structure of MOSFET, manufacturing method, power device, electronic equipment, it is a semiconductor technical field, through including epitaxial layer, channel layer, active layer, grid structure, the first ditch groove, the first conductive layer, the first dielectric layer, metal column, floating junction and the first insulating layer; the semiconductor device comprises an epitaxial layer, a channel layer, an active layer, a gate structure, a first trench, a first conductive layer, a metal column, a floating junction, a first insulating layer and a metal column, wherein the channel layer is arranged on the upper surface of the epitaxial layer, the active layer is arranged on the upper surface of the channel layer, the gate structure longitudinally penetrates through the active layer and the channel layer downwards from the upper surface of the active layer, the first trench longitudinally penetrates through the active layer and the channel layer downwards from the upper surface of the active layer, the first conductive layer covers the inner surface of the side wall of the first trench, the first dielectric layer covers the inner surface of the side wall of the first conductive layer, the metal column is filled in the first dielectric layer, the floating junction is arranged at the bottom of the first trench, the first insulating layer is arranged at the top of the first trench, and the internal resistance of the MOSFET is reduced, and the longitudinal pressure resistance and the transverse pressure resistance are improved.

Inventors

ZHANG FENG
LIU JIE

Assignees

深圳芯能半导体技术有限公司

Dates

Publication Date: 20260505
Application Date: 20220909

Claims (10)

1. A structure of a kind of MOSFET, characterized by comprising the following steps: An epitaxial layer; a channel layer provided on an upper surface of the epitaxial layer; An active layer disposed on an upper surface of the channel layer; a gate structure passing longitudinally downward through the active layer and the channel layer from an upper surface of the active layer; A first trench passing longitudinally downward through the active layer and the channel layer from an upper surface of the active layer; a first conductive layer covering the inner surface of the side wall of the first groove; A first dielectric layer covering the inner surface of the side wall of the first conductive layer; a metal pillar filled inside the first dielectric layer; A floating junction at the bottom of the first trench; a first insulating layer on top of the first trench; The epitaxial layer is an N-type epitaxial layer, the channel layer is a P-type channel layer, the active layer is a P-type active layer, and the floating junction is a P-type floating junction, or The epitaxial layer is a P-type epitaxial layer, the channel layer is an N-type channel layer, the active layer is an N-type active layer, and the floating junction is an N-type floating junction.
2. The structure of a MOSFET of claim 1, further comprising: a second trench longitudinally penetrating the first insulating layer and the active layer downward from an upper surface of the first insulating layer; a first metal layer located on the upper surface of the first insulating layer and on the top of the second trench; the bottom of the second groove is in contact with the upper surface of the channel layer, and the second groove is filled with metal.
3. The structure of the MOSFET of claim 2 wherein said gate structure comprises: a third trench extending longitudinally downward from the upper surface of the insulator through the first insulator layer, the active layer and the channel layer; a second dielectric layer covering the inner surfaces of the side walls of the third grooves; And the conductive column is filled in the second dielectric layer.
4. The structure of a MOSFET of claim 3 wherein said first dielectric layer and said second dielectric layer comprise silicon dioxide and silicon nitride and wherein said first conductive layer and said conductive post comprise polysilicon.
5. The structure of the MOSFET of claim 1, wherein the MOSFET comprises a field effect transistor, wherein the channel layer is a gate of the field effect transistor, wherein the epitaxial layer is a drain of the field effect transistor, and wherein the active layer is a source of the field effect transistor; The floating junction and the epitaxial layer form a superjunction structure.
6. A method of manufacturing a MOSFET, the method comprising: Forming an epitaxial layer; removing a portion of the epitaxial layer to form a first trench and a third trench; Forming a second dielectric layer on the upper surface of the third groove; Forming a first conductive layer on the side surface of the first trench, and filling the inside of the second dielectric layer to form a conductive column; Ion implantation is performed on the bottom of the first groove and the upper surface of the epitaxial layer to form a floating junction and a channel layer, wherein the floating junction is positioned at the bottom of the first groove, and the channel layer is positioned on the upper surface of the epitaxial layer; Filling the inside of the first conductive layer to form a dielectric pillar, and forming a second insulating layer on the upper surface of the channel layer; etching back the second insulating layer to expose the channel layer; Ion implantation is performed on the upper surface of the channel layer to form an active layer; forming a first insulating layer on an upper surface of the active layer; Removing the central region of the dielectric column to form a fourth groove, and removing part of the first insulating layer and part of the active layer to form a second groove; filling the fourth groove to form a metal column, filling the second groove, and forming a first metal layer on the upper surface of the first insulating layer; The epitaxial layer is an N-type epitaxial layer, the channel layer is a P-type channel layer, the active layer is a P-type active layer, and the floating junction is a P-type floating junction, or The epitaxial layer is a P-type epitaxial layer, the channel layer is an N-type channel layer, the active layer is an N-type active layer, and the floating junction is an N-type floating junction.
7. The method of manufacturing a MOSFET according to claim 6, wherein said removing a portion of said epitaxial layer to form a first trench and a third trench comprises: forming a silicon dioxide layer on the upper surface of the epitaxial layer; removing a part of the silicon dioxide layer to form a mask layer, wherein the mask layer is provided with a fifth groove and a sixth groove; Removing part of the epitaxial layer by taking the mask layer as a mask to form the first groove and the third groove; and removing the mask layer.
8. The method of manufacturing a MOSFET according to claim 6, wherein forming a first conductive layer on a side surface of the first trench and filling an interior of the second dielectric layer to form a conductive pillar comprises: filling the inside of the second dielectric layer to form a conductive column, and forming a second conductive layer on the surface of the first groove and the upper surface of the epitaxial layer; Etching back an upper surface of the second conductive layer and leaving the second conductive layer on side surfaces of the first trench to form the first conductive layer.
9. A power device comprising a plurality of MOSFET structures according to any one of claims 1 to 5 arranged in sequence.
10. An electronic device comprising a structure of a MOSFET according to any one of claims 1 to 5.

Description

MOSFET structure, manufacturing method, power device and electronic equipment Technical Field The application belongs to the technical field of semiconductors, and particularly relates to a MOSFET structure, a manufacturing method, a power device and electronic equipment. Background The related Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device comprises an epitaxial layer, a channel layer, an active layer and an insulating layer which are arranged downwards and upwards, a trench, a dielectric layer and a conductive column, wherein the trench longitudinally penetrates through the active layer and the channel layer downwards from the upper surface of the active layer, the dielectric layer covers the inner surface of the side wall of the first trench and the upper surface of the bottom of the first trench, and the conductive column is positioned inside the dielectric layer. The epitaxial layer is thicker and only serves as a drain electrode, so that the related defects of low lateral voltage withstand capability and reverse voltage withstand capability of the MOSFET and large internal resistance are caused. Disclosure of Invention The application aims to provide a structure and a manufacturing method of a MOSFET, a power device and electronic equipment, and aims to solve the problems of low transverse voltage withstand capability and reverse voltage withstand capability and large internal resistance of related MOSFETs. The embodiment of the application provides a MOSFET structure, which comprises: An epitaxial layer; a channel layer provided on an upper surface of the epitaxial layer; An active layer disposed on an upper surface of the channel layer; a gate structure passing longitudinally downward through the active layer and the channel layer from an upper surface of the active layer; A first trench passing longitudinally downward through the active layer and the channel layer from an upper surface of the active layer; a first conductive layer covering the inner surface of the side wall of the first groove; A first dielectric layer covering the inner surface of the side wall of the first conductive layer; a metal pillar filled inside the first dielectric layer; A floating junction at the bottom of the first trench; And a first insulating layer positioned on top of the first trench. In one embodiment, the method further comprises: a second trench longitudinally penetrating the first insulating layer and the active layer downward from an upper surface of the first insulating layer; a first metal layer located on the upper surface of the first insulating layer and on the top of the second trench; the bottom of the second groove is in contact with the upper surface of the channel layer, and the second groove is filled with metal. In one embodiment, the gate structure includes: a third trench extending longitudinally downward from the upper surface of the insulator through the first insulator layer, the active layer and the channel layer; a second dielectric layer covering the inner surfaces of the side walls of the third grooves; And the conductive column is filled in the second dielectric layer. In one embodiment, the epitaxial layer is an N-type epitaxial layer, the channel layer is a P-type channel layer, the active layer is a P-type active layer, and the floating junction is a P-type floating junction, or The epitaxial layer is a P-type epitaxial layer, the channel layer is an N-type channel layer, the active layer is an N-type active layer, and the floating junction is an N-type floating junction. In one embodiment, the materials of the first dielectric layer and the second dielectric layer comprise silicon dioxide and silicon nitride, and the materials of the first conductive layer and the conductive pillars comprise polysilicon. In one embodiment, the MOSFET comprises a field effect transistor, wherein the channel layer is a grid electrode of the field effect transistor, the epitaxial layer is a drain electrode of the field effect transistor, and the active layer is a source electrode of the field effect transistor; The floating junction and the epitaxial layer form a superjunction structure. The embodiment of the application also provides a manufacturing method of the MOSFET, which comprises the following steps: Forming an epitaxial layer; removing a portion of the epitaxial layer to form a first trench and a third trench; Forming a second dielectric layer on the upper surface of the third groove; Forming a first conductive layer on the side surface of the first trench, and filling the inside of the second dielectric layer to form a conductive column; Ion implantation is performed on the bottom of the first groove and the upper surface of the epitaxial layer to form a floating junction and a channel layer, wherein the floating junction is positioned at the bottom of the first groove, and the channel layer is positioned on the upper surface of the epitaxial layer; Filling the inside of the