CN-115495909-B - Aging prediction modeling method suitable for DRAM peripheral transistor under on-state arbitrary stress condition

CN115495909BCN 115495909 BCN115495909 BCN 115495909BCN-115495909-B

Abstract

The invention discloses an aging prediction modeling method suitable for a DRAM peripheral transistor under any stress condition in an on state. According to the dominant stress areas of different types of defects, the data are extracted from the dominant stress areas of the defects to determine the corresponding parameters of the defects Nit1, not-e, not-h and Nit2, all the obtained parameters are integrated, and an arbitrary stress condition is input, so that the aging amount of the device under the condition at any moment can be obtained. The invention can carry out integral calibration and parameter value fine adjustment with all experimental data, so that the consistency of the model and the experimental data is optimal. The invention can realize the long-time aging prediction of the device under different stress conditions (different combinations of Vg/Vd) in an on state. The method has the advantages of high reliability, good prediction accuracy, strong practicability and the like.

Inventors

JI ZHIGANG
WANG DA
WANG RUNSHENG
REN PENGPENG

Assignees

北京超弦存储器研究院
上海交通大学
北京大学

Dates

Publication Date: 20260505
Application Date: 20220923

Claims (10)

1. An aging prediction modeling method suitable for a DRAM peripheral transistor under any stress condition in an on state comprises the following steps: 1) Dividing all working voltage areas of the DRAM peripheral transistor into stress areas dominated by different defect types according to all defect types existing in a grid electrode oxide layer of the DRAM peripheral transistor and the influence of various defects on the device when different voltages are applied to the device, and establishing a physical model of the device threshold voltage degradation caused by different defects; 2) Respectively selecting a plurality of groups of data under the high electric field stress condition of different V D /V G from the stress area dominated by different defect types, wherein the drain voltage |V D | or the grid voltage |V G | is larger than the typical working voltage by 3V, and determining the model fitting parameter values representing corresponding defects in the area by realizing the matching of the model prediction effect and the measured data to obtain the threshold voltage offset generated by different defect types under any voltage and any working time; 3) Integrating calculation formulas for representing the degradation amount of threshold voltage caused by all defect types to obtain a complete aging model, and verifying the matching effect of the degradation amount of the threshold voltage of the device calculated by the model and experimental data actually measured under the condition of low electric field stress, namely, drain voltage |V D | and gate voltage |V G | are smaller than or equal to typical working voltage 3V; 4) And 3, obtaining an aging model by using the step 3, and inputting V D /V G stress and aging time with any length under any on-state condition, wherein the grid voltage |V G | under the on-state condition is larger than the threshold voltage of 0.85V, so that the degradation amount of the device under the on-state condition can be predicted.
2. The aging prediction modeling method applicable to the DRAM peripheral transistor under the on-state arbitrary stress condition according to claim 1, wherein all the operating voltage areas of the DRAM peripheral transistor are divided into: interface state defect Nit1 dominates device burn-in Region1, oxide electron trap Not-e dominates device burn-in Region2, oxide hole trap Not-h dominates device burn-in Region3, and interface state defect Nit2 dominates device burn-in Region4.
3. The aging prediction modeling method applicable to the DRAM peripheral transistor under any stress condition in the on state of claim 2, wherein a plurality of groups of data under different V D /V G stress conditions are selected from region1, substituted into the formula (1) of defect Nit1, and the corresponding fitting parameter a 1 、B 1 、C 1 is determined by experimental data, so as to obtain the threshold voltage offset generated by N it1 : (1) Where t is the time of stressing, V G and V D represent the applied gate and drain stresses, N 1 is the time constant of defect N it1 , and Δv th_Nit1 represents the threshold voltage shift produced by N it1 .
4. The method for aging prediction modeling under any stress condition in the on-state of a DRAM peripheral transistor as defined in claim 2, wherein the determination of Not-E uses a tensile index model to model the same, wherein a plurality of sets of data under different V D /V G stress conditions are selected from region2, substituted into the corresponding formulas (2), (3) and (4) of defective Not-E, and the values of the corresponding fitting parameters E 1 、E 2 , p and q are determined through experimental data to obtain the threshold voltage offset generated by Not-E, (2) In formula (2), D represents the total density of defects Not-e, τ represents the time constant of the defect, β represents the distribution width of the defect type, t is the time of applying stress, Δv th_Not-e represents the threshold voltage shift amount generated by Not-e, and D and τ, in turn, respectively conform to the following formulas: (3) (4) V G and V D represent applied gate and drain stress.
5. The aging prediction modeling method applicable to the on-state arbitrary stress condition of the DRAM peripheral transistor according to claim 2, wherein a plurality of groups of data under different V D /V G stress conditions are selected in region3, substituted into the formula (5) of the defect Not-h, and the corresponding fitting parameter a 2 、B 2 、C 2 is determined by experimental data to obtain the threshold voltage offset generated by Not-h: (5) Where t is the time of stress application, V G and V D represent the gate and drain stress applied, n 2 is the time constant of defect Not-h, and DeltaV th_Not-h represents the threshold voltage shift produced by Not-h.
6. The aging prediction modeling method applicable to the DRAM peripheral transistor under any stress condition in the on state of claim 2, wherein the data under the stress condition of a plurality of groups of different V D /V G is selected in region4, substituted into the formula (6) of the defect Nit2, and the corresponding fitting parameter a 3 、B 3 、C 3 is determined by experimental data, so as to obtain the threshold voltage offset generated by Nit 2: (6) Where t is the time of stress application, V G and V D represent the applied gate and drain stress, n 3 is the time constant of defect Nit2, and Δv th_Nit2 represents the threshold voltage shift produced by Nit 2.
7. The aging prediction modeling method for an on-state arbitrary stress condition of a DRAM peripheral transistor according to claim 4, wherein the value of the fitting parameter a 1 、B 1 、C 1 is substituted into the formula (1) and added to the formula (2).
8. The aging prediction modeling method for an on-state arbitrary stress condition of a DRAM peripheral transistor according to claim 5, wherein the value of the fitting parameter a 1 、B 1 、C 1 is substituted into the formula (1) and added to the formula (5).
9. The method for modeling aging prediction under any stress condition in the on state of a DRAM peripheral transistor according to claim 6, wherein the value of the fitting parameter a 2 、B 2 、C 2 is substituted into the formula (5) and added to the formula (6).
10. The aging prediction modeling method applicable to the DRAM peripheral transistor under any stress condition in the on state according to claim 2, wherein the stress value range of V D /V G in Region1 is 0.5 x|V D | < |V G | < |V D |, the stress value range of V D /V G in Region2 is |V G | < 0.5* |V D |, the stress value range of V D /V G in Region3 is |V G | > |V D |, and the stress value range of V D /V G in Region4 is |V D | < 0.8V.

Description

Aging prediction modeling method suitable for DRAM peripheral transistor under on-state arbitrary stress condition Technical Field The invention relates to the technical field of DRAM peripheral devices, in particular to an aging prediction modeling method suitable for an on-state arbitrary stress condition of a DRAM peripheral transistor. Background As process nodes continue to drop, device leakage becomes more serious. Under the current sub-20 nm DRAM technology, various large DRAM manufacturers introduce high dielectric constant (high-k) materials onto the transistor gate oxide layer to inhibit the leakage problem of the device. But with the consequent introduction of a large number of defects in the gate oxide layer and the introduction of a large number of Si-H bonds during annealing, the Hot Carrier Degradation (HCD) phenomenon of the device is exacerbated. In addition, although the operating voltage of the DRAM is continuously reduced, in order to have a larger driving capability when the transistor is turned on, a high voltage of, for example, 3V is required to be internally generated, which requires the use of a thick oxygen device to achieve the corresponding function. In recent years, serious HCD phenomena on thick oxygen devices under the sub-20 nm process are reported by foreign DRAM giant, sea power, and American light disputes, and serious HCD phenomena are also found on thick oxygen PMOS by the long Xin of domestic DRAM manufacturers. It is therefore desirable to predict the long-term aging of HCD phenomena. Current aging models for sub-20 nm DRAM processes include the defect-based physical model proposed by 20-year halibut (Seung-Geun Jung published in EDL) and the mathematical model used by samsung 21 that only considers aging time (d.son published in IRPS). The method only stays at the physical mechanism level, a corresponding mathematical model is not established to realize the aging prediction of the device, and the method only considers the influence of aging time under specific stress voltage (Vg=0.5 Vd) and cannot be used in a wide range of the whole stress voltage area. Although a complete aging model can be used in the logic device, the aging rule is different due to the defect type difference between the DRAM prepared by the gate-first process and the logic device prepared by the traditional gate-last process, and the model proposed on the traditional logic device cannot be directly put into the DRAM device for use. In summary, the prior art solution cannot achieve a good prediction effect on the PMOS of the DRAM peripheral device, and a complete HCD model is required to accurately predict the long-term degradation of the DRAM peripheral device caused by HCD at any turn-on voltage. Disclosure of Invention Aiming at the problems in the prior art, the invention provides an aging prediction modeling method suitable for a DRAM peripheral transistor under any stress condition in an on state. The technical scheme provided by the invention is as follows: An aging prediction modeling method suitable for a DRAM peripheral transistor under any stress condition in an on state comprises the following steps: 1) Dividing all possible working voltage areas of the DRAM peripheral transistor into stress areas dominated by different defect types according to all possible defect types in a grid electrode oxide layer of the DRAM peripheral transistor and the influence of various defects on the device when different voltages are applied to the device, and establishing a physical model of degradation of threshold voltage of the device caused by different defects; 2) Respectively selecting a plurality of groups of data under the high electric field stress condition of different V D/VG from the stress area dominated by different defect types, wherein the drain voltage |V D | or the grid voltage |V G | is larger than the typical working voltage by 3V, and determining the model fitting parameter values representing corresponding defects in the area by realizing the matching of the model prediction effect and the measured data to obtain the threshold voltage offset generated by different defect types under any voltage and any working time; 3) Integrating calculation formulas for representing the degradation amount of threshold voltage caused by all defect types to obtain a complete aging model, and verifying the matching effect of the degradation amount of the threshold voltage of the device calculated by the model and experimental data actually measured under the condition of low electric field stress, namely, drain voltage |V D | and gate voltage |V G | are smaller than or equal to typical working voltage 3V; 4) And 3) inputting V D/VG stress and ageing time with any length under any on-state condition by using the ageing model obtained in the step 3), wherein the grid voltage |V G | under the on-state condition is larger than the threshold voltage of 0.85V, and the degradation amount of the device under