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CN-115498981-B - Monostable circuit

CN115498981BCN 115498981 BCN115498981 BCN 115498981BCN-115498981-B

Abstract

The embodiment of the disclosure provides a monostable circuit, which comprises a monostable main circuit and a shielding time window circuit, wherein the monostable main circuit is configured to receive an input signal of the monostable circuit, feedback of an output signal of the monostable circuit and a time window signal output by the shielding time window circuit through a NOR gate, then the output signal is obtained after passing through a first RC delay circuit and a logic gate, the time window signal is a signal resisting interference of abnormal pulses of the input signal to the output signal, and the shielding time window circuit is configured to receive feedback of the output signal and then obtain the time window signal after passing through a second RC delay circuit and the logic gate. The problem that the existing monostable circuit can be triggered by mistake due to abnormal pulses of input signals is solved.

Inventors

  • ZHANG LIDI

Assignees

  • 圣邦微电子（北京）股份有限公司

Dates

Publication Date
20260512
Application Date
20220901

Claims (10)

  1. 1. The monostable circuit is characterized by comprising a monostable main circuit and a shielding time window circuit; The monostable main circuit is configured to receive an input signal of the monostable circuit, feedback of an output signal of the monostable circuit and a time window signal output by the shielding time window circuit through a NOR gate, and then obtain the output signal after passing through a first RC delay circuit and a logic gate, wherein the time window signal is a signal resisting the interference of abnormal pulses of the input signal on the output signal; The shielding time window circuit is configured to receive the feedback of the output signal, and then obtains the time window signal after passing through the second RC delay circuit and the logic gate.
  2. 2. The monostable of claim 1 wherein said monostable master circuit comprises said nor gate, said first RC delay circuit, a first nor gate, a second nor gate, a nand gate; The input end of the NOR gate receives the input signal, the feedback of the output signal and the time window signal, and the output end of the NOR gate is connected with the first RC delay circuit; The first RC delay circuit is configured to delay signals through charging and discharging of a capacitor, and the output end of the first RC delay circuit is connected with the input end of the first NOT gate; The output end of the first NOT gate is connected with one input end of the NAND gate, the other input end of the NAND gate is connected with the input signal, and the output end of the NAND gate is connected with the input end of the second NOT gate; The output end of the second NOT gate outputs the output signal.
  3. 3. The monostable of claim 2 wherein said masking time window circuit comprises said second RC delay circuit, a third NOT gate; The second RC delay circuit is configured to delay signals through charging and discharging of a capacitor, the input end of the second RC delay circuit receives feedback of the output signals, the output end of the second RC delay circuit is connected with the input end of the third NOT gate, and the output end of the third NOT gate outputs the time window signals.
  4. 4. The monostable of claim 3 wherein the first RC delay circuit comprises a first transistor, a second transistor, a first resistor, a first capacitor; The grid electrodes of the first transistor and the second transistor are both connected with the output end of the NOR gate, the source electrode of the first transistor is connected with the power supply end, the source electrode of the second transistor is connected with the grounding end, the drain electrode of the first transistor is connected with one end of the first resistor, the drain electrode of the second transistor is connected with the other end of the first resistor, the first transistor is a P-type transistor, and the second transistor is an N-type transistor; The first capacitor is connected with the second transistor in parallel, one end of the first capacitor is connected with the drain electrode of the second transistor, and the other end of the first capacitor is connected with the source electrode of the second transistor; An intermediate node between the first resistor and the second transistor is connected to the input of the first NOT gate.
  5. 5. The monostable of claim 4 wherein the second RC delay circuit comprises a third transistor, a fourth transistor, a second resistor, a second capacitor; the gates of the third transistor and the fourth transistor both receive feedback of the output signal, the source of the third transistor is connected to a power supply end, the source of the fourth transistor is connected to a ground end, the drain of the third transistor is connected to one end of the second resistor, the drain of the fourth transistor is connected to the other end of the second resistor, the third transistor is a P-type transistor, and the fourth transistor is an N-type transistor; the second capacitor is connected with the fourth transistor in parallel, one end of the second capacitor is connected with the drain electrode of the fourth transistor, and the other end of the second capacitor is connected with the source electrode of the fourth transistor; an intermediate node between the second resistor and the fourth transistor is connected to the input of the third NOT gate.
  6. 6. The monostable of claim 5 wherein the discharge time constant of the second RC delay circuit is less than the charge time length of the first RC delay circuit.
  7. 7. The monostable of claim 6 wherein the initial low level of the input signal is greater than a first predetermined period of time during which the third transistor and the second resistor pull the input of the third not gate high.
  8. 8. The monostable of claim 7, wherein a sum of a discharge time period of the second RC delay circuit and a charge time period of the second RC delay circuit is less than or equal to a second preset time period, the second preset time period being a preset interval time period for triggering the monostable.
  9. 9. The monostable of claim 8 wherein the monostable is a monostable in a low speed chip.
  10. 10. The monostable circuit is characterized by comprising a NOR gate, first to fourth transistors, a first resistor, a second resistor, a first capacitor, a second capacitor, a first NOT gate, a second NOT gate, a third NOT gate and a NAND gate; The input end of the NOR gate receives an input signal of the monostable circuit, feedback of an output signal of the monostable circuit and a time window signal, and the output end of the NOR gate is connected with the grid electrode of the first transistor and the grid electrode of the second transistor; the source electrode of the first transistor is connected with a power supply end, the source electrode of the second transistor is connected with a ground end, the drain electrode of the first transistor is connected with one end of the first resistor, the drain electrode of the second transistor is connected with the other end of the first resistor, the first transistor is a P-type transistor, and the second transistor is an N-type transistor; The first capacitor is connected with the second transistor in parallel, one end of the first capacitor is connected with the drain electrode of the second transistor, the other end of the first capacitor is connected with the source electrode of the second transistor, the intermediate node between the first resistor and the second transistor is connected with the input end of the first NOT gate, The output end of the first NOT gate is connected with one input end of the NAND gate, the other input end of the NAND gate is connected with the input signal, the output end of the NAND gate is connected with the input end of the second NOT gate, and the output end of the second NOT gate outputs the output signal; The grid electrode of the third transistor and the grid electrode of the fourth transistor receive feedback of the output signal, the source electrode of the third transistor is connected with a power supply end, the source electrode of the fourth transistor is connected with a grounding end, the drain electrode of the third transistor is connected with one end of the second resistor, the drain electrode of the fourth transistor is connected with the other end of the second resistor, the third transistor is a P-type transistor, and the fourth transistor is an N-type transistor; the second capacitor is connected with the fourth transistor in parallel, one end of the second capacitor is connected with the drain electrode of the fourth transistor, and the other end of the second capacitor is connected with the source electrode of the fourth transistor; and an intermediate node between the second resistor and the fourth transistor is connected with the input end of the third NOT gate, and the output end of the third NOT gate outputs the time window signal.

Description

Monostable circuit Technical Field Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to monostable circuits. Background One-shot circuits (monostables) are widely used for pulse shaping, delay (producing output pulses that lag the trigger pulses) and timing (producing pulse signals of a fixed time width). The delay effect is realized by charging and discharging of the RC circuit, and the time length depends on circuit parameters. In some low-speed logic chips, it is often desirable to allow the next One-Shot to be triggered after a longer time T after One-Shot (the output signal of the One-Shot circuit) trigger. For the traditional One-Shot circuit, in the interval time T, abnormal pulses may occur to the input signal of the One-Shot circuit, and the abnormal pulses may trigger the One-Shot signal by mistake, so that practical application is affected. Disclosure of Invention The embodiments described herein provide a monostable circuit to solve the problem that the existing monostable circuit may be triggered by an abnormal pulse of an input signal. The monostable circuit comprises a monostable main circuit and a shielding time window circuit, wherein the monostable main circuit is configured to receive an input signal of the monostable circuit, feedback of an output signal of the monostable circuit and a time window signal output by the shielding time window circuit through a NOR gate, then the output signal is obtained after the output signal passes through a first RC delay circuit and a logic gate, the time window signal is a signal resisting interference of abnormal pulses of the input signal to the output signal, and the shielding time window circuit is configured to receive feedback of the output signal and then obtain the time window signal after the output signal passes through a second RC delay circuit and the logic gate. The monostable main circuit comprises a NOR gate, a first RC delay circuit, a first NOT gate, a second NOT gate and a NAND gate, wherein the input end of the NOR gate receives the input signal, feedback of the output signal and the time window signal, the output end of the NOR gate is connected with the first RC delay circuit, the first RC delay circuit is configured to delay signals through charge and discharge of a capacitor, the output end of the first RC delay circuit is connected with the input end of the first NOT gate, the output end of the first NOT gate is connected with one input end of the NAND gate, the other input end of the NAND gate is connected with the input signal, the output end of the NAND gate is connected with the input end of the second NOT gate, and the output end of the second NOT gate outputs the output signal. Optionally, the shielding time window circuit comprises a second RC delay circuit and a third NOT gate, wherein the second RC delay circuit is configured to delay signals through charge and discharge of a capacitor, the input end of the second RC delay circuit receives feedback of the output signals, the output end of the second RC delay circuit is connected with the input end of the third NOT gate, and the output end of the third NOT gate outputs the time window signals. The first RC delay circuit comprises a first transistor, a second transistor, a first resistor and a first capacitor, wherein grid electrodes of the first transistor and the second transistor are connected with an output end of the NOR gate, a source electrode of the first transistor is connected with a power supply end, a source electrode of the second transistor is connected with a grounding end, a drain electrode of the first transistor is connected with one end of the first resistor, a drain electrode of the second transistor is connected with the other end of the first resistor, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the first capacitor is connected with the second transistor in parallel, one end of the first capacitor is connected with the drain electrode of the second transistor, the other end of the first capacitor is connected with the source electrode of the second transistor, and an intermediate node between the first resistor and the second transistor is connected with an input end of the first NOR gate. The second RC delay circuit comprises a third transistor, a fourth transistor, a second resistor and a second capacitor, wherein grid electrodes of the third transistor and the fourth transistor are used for receiving feedback of the output signals, a source electrode of the third transistor is connected with a power end, a source electrode of the fourth transistor is connected with a grounding end, a drain electrode of the third transistor is connected with one end of the second resistor, a drain electrode of the fourth transistor is connected with the other end of the second resistor, the third transistor is a P-type transistor, the fourth transistor is a