CN-115509778-B - Programmable watchdog and timer logic IP design method for Feiteng processor

Abstract

The invention discloses a programmable watchdog and timer logic IP design method for a Feiteng processor, wherein a watchdog overtime time register is designed in the watchdog logic IP, watchdog reset logic is used for carrying out internal counting according to the set time and combining the states of a watchdog feeding signal and a watchdog enabling signal, and after the counter reaches a value corresponding to the overtime time, the watchdog reset signal is output, so that the programmability of the watchdog overtime time is realized. The timer logic IP realizes the counting control of the programmable timer by instantiating the timer period, emptying the timer and starting a register of the timer, and the logic chip outputs external interrupt to the domestic Feiteng processor after the counter reaches a set value. The invention effectively expands the timer resources of the domestic embedded system based on the Feiteng processor.

Inventors

• Jia bolun
• CAI YI
• ZHOU MINGJIE

Assignees

• 中国航空工业集团公司洛阳电光设备研究所

Dates

Publication Date

20260508

Application Date

20220809

Claims (1)

1. 1. A programmable watchdog and timer logic IP design method for a Feiteng processor, comprising the steps of: step 1, watchdog reset control logic; The watchdog reset control logic is used for carrying out time sequence control on watchdog reset output, and writing timeout time into a watchdog timeout time register through an LBC interface of the Feiteng processor under the condition that a watchdog timeout configuration chip option Wdg _time_csn is effective; Under the application state, reading the states of a watchdog feeding signal Wdg _wdi and a watchdog enabling register wdg _en, counting through a logic reference clock, triggering watchdog reset when the count value reaches the value configured by a watchdog timeout time register, and resetting a Feiteng processor and interfaces; Step2, a timer reset control logic; The Timer is realized by instantiation in the logic IP, and the LBC interface of the Feiteng processor is used for configuring a Timer period timer_period, a Timer emptying timer_clear and a Timer starting control timer_start register; When the timer emptying signal is invalid and the timer starting signal is valid, the timer counting register is accumulated and counted, and when the counting value reaches the set value of the timer period register, the external interrupt is output to the Feiteng processor; Step 3, a Feiteng processor; the Feiteng processor is used for receiving a reset signal output by the watchdog reset logic, realizing self reset, reloading and running software, receiving a timer interrupt signal output by a timer exemplified in the logic IP through external interrupt, entering an interrupt service routine and executing an interrupt task.

Description

Programmable watchdog and timer logic IP design method for Feiteng processor Technical Field The invention belongs to the technical field of embedded design, and particularly relates to a programmable watchdog and timer logic IP design method. Background The watchdog reset function is used in an embedded system for automatic reset control in the event of an application program execution exception. The watchdog reset chip can be used for realizing the hardware watchdog reset function, but the timeout time of watchdog reset is limited by the hardware state of the watchdog reset chip, and is generally fixed time. With the change of application scenes, the aviation onboard embedded system needs the watchdog reset function to have programmability, and the watchdog timeout time can be controlled according to the system needs by instantiating the logic IP, so that the expansibility and the flexibility of the watchdog logic IP are improved. The programmable timer can periodically trigger timer interrupt in the embedded system through software set time, so that the processor enters an interrupt service routine to process interrupt tasks. At present, the domestic Feiteng processor has no internal timer, and the timer interrupt cannot be realized. In order to expand the functions of the embedded system based on the domestic Feiteng processor, the timer interrupt control can be realized by instantiating the logic IP. Disclosure of Invention In order to overcome the defects of the prior art, the invention provides a programmable watchdog and timer logic IP design method for a Feiteng processor, a watchdog overtime time register is designed in the watchdog logic IP, watchdog reset logic is used for carrying out internal counting according to set time and combining states of a watchdog feeding signal and a watchdog enabling signal, and after the counter reaches a value corresponding to the overtime time, the watchdog reset signal is output, so that the programmability of the watchdog overtime time is realized. The timer logic IP realizes the counting control of the programmable timer by instantiating the timer period, emptying the timer and starting a register of the timer, and the logic chip outputs external interrupt to the domestic Feiteng processor after the counter reaches a set value. The invention effectively expands the timer resources of the domestic embedded system based on the Feiteng processor. The technical scheme adopted for solving the technical problems is as follows: step 1, watchdog reset control logic; The watchdog reset control logic is used for carrying out time sequence control on watchdog reset output, and writing timeout time into a watchdog timeout time register through an LBC interface of the Feiteng processor under the condition that a watchdog timeout configuration chip option Wdg _time_csn is effective; Under the application state, reading the states of a watchdog feeding signal Wdg _wdi and a watchdog enabling register wdg _en, counting through a logic reference clock, triggering watchdog reset when the count value reaches the value configured by a watchdog timeout time register, and resetting a Feiteng processor and interfaces; Step2, a timer reset control logic; The Timer is realized by instantiation in the logic IP, and the LBC interface of the Feiteng processor is used for configuring a Timer period timer_period, a Timer emptying timer_clear and a Timer starting control timer_start register; When the timer emptying signal is invalid and the timer starting signal is valid, the timer counting register is accumulated and counted, and when the counting value reaches the set value of the timer period register, the external interrupt is output to the Feiteng processor; Step 3, a Feiteng processor; the Feiteng processor is used for receiving a reset signal output by the watchdog reset logic, realizing self reset, reloading and running software, receiving a timer interrupt signal output by a timer exemplified in the logic IP through external interrupt, entering an interrupt service routine and executing an interrupt task. The beneficial effects of the invention are as follows: The invention realizes the watchdog programmability of the domestic embedded system and expands the timer function of the Feiteng processor through the logic IP. Drawings Fig. 1 is a logical IP block diagram of the SPI interface of the present invention. Detailed Description The invention will be further described with reference to the drawings and examples. The invention aims to provide an extended programmable watchdog and timer logic IP design for a domestic Feiteng processor, which realizes the settable watchdog reset timeout time and the extension of the domestic Feiteng processor timer function. In order to achieve the purpose, the invention is achieved by adopting a standard verilog language and is realized based on a domestic CPLD hardware platform. The invention relates to an extended programmable watchdog and time