CN-115513123-B - Silicon-on-insulator structure and forming method thereof

CN115513123BCN 115513123 BCN115513123 BCN 115513123BCN-115513123-B

Abstract

The invention provides a silicon-on-insulator structure and a forming method thereof, wherein the forming method of the silicon-on-insulator structure increases the normal temperature bonding strength in the bonding process through activating treatment, reduces the temperature required by the subsequent reinforcing process, thereby reducing the thermal diffusion of heterogeneous components in an etching stop layer, ensuring the clear interface between the etching stop layer and a device layer, further avoiding the deterioration of the thickness uniformity of the device layer after the etching stop layer is removed in the subsequent process, controlling the uniformity of the device layer after etching through two selective etching processes, leading the thickness uniformity of the device layer of the finally obtained silicon-on-insulator structure to be less than 10%, and leading the surface of the device layer to have a porous morphology without high-frequency etching fluctuation through the formation and removal of a sacrificial oxide layer.

Inventors

WEI XING
WANG ZIWEN
Dai Rongwang
CHEN MENG
XU HONGTAO

Assignees

上海新昇半导体科技有限公司
中国科学院上海微系统与信息技术研究所

Dates

Publication Date: 20260508
Application Date: 20221104

Claims (8)

1. A method of forming a silicon-on-insulator structure, comprising the steps of: step S1, providing a first substrate and a second substrate, wherein the first substrate is provided with a first front surface and a first back surface which are oppositely arranged, an etching stop layer and a device layer are sequentially formed on the first front surface, and the second substrate is provided with a second front surface; s2, performing oxygen plasma activation treatment on the surfaces of the second front surface and the device layer, bonding the first substrate and the second substrate, enabling the second front surface to face the device layer, and performing low-temperature reinforcement treatment at 300-500 ℃; step S3, thinning the first substrate from the first back surface by using mechanical grinding; selectively etching the rest of the first substrate for the first time by a first etchant, and stopping etching on the etching stop layer; Etching the etch stop layer by a second etchant for a second time and etching the surface of the device layer to form a porous layer on the surface of the device layer, and And S4, generating a sacrificial oxide layer on the device layer, filling and covering the porous layer by the sacrificial oxide layer, and removing the sacrificial oxide layer and the porous layer through a wet etching process to obtain the silicon-on-insulator structure.
2. The method of forming of claim 1, wherein step S1 comprises: Providing a first substrate, wherein the first substrate is provided with a first front surface and a first back surface which are oppositely arranged; Forming an etch stop layer on the first front side; forming a device layer on the etch stop layer; Providing a second substrate, wherein a polysilicon capture layer is formed on the surface of the second substrate, and the surface of the polysilicon capture layer is the second front surface; forming an insulating layer by an oxidation process, and The insulating layer is located on the surface of the device layer, or the insulating layer comprises a first insulating layer and a second insulating layer, the first insulating layer is located on the surface of the device layer, and the second insulating layer is located on the second front surface.
3. The method of forming of claim 1, wherein the consolidation process is performed for a process time of no more than 4 hours.
4. The method of claim 1, wherein the first etchant is TMAH, the concentration of the first etchant is not higher than 25%, and the etching temperature is 55 ℃ to 70 ℃.
5. The method of claim 1, wherein the second etchant is a mixed solution of HF, HNO 3 , and Hac, or a mixed solution of HF, H 2 O 2 , and Hac.
6. The method of forming of claim 1, wherein step S4 comprises: oxidizing the surface of the device layer in dry oxygen, wet oxygen or a dry oxygen and wet oxygen combined atmosphere to generate a sacrificial oxide layer on the device layer, wherein the sacrificial oxide layer fills and covers the porous layer; Removing the sacrificial oxide layer and the porous layer by wet etching process to obtain a silicon-on-insulator structure, and And performing roughness optimization treatment on the surface of the device layer through heat treatment.
7. The method of forming of claim 6, wherein the wet etching process uses an HF solution having a concentration of less than 20%.
8. A silicon-on-insulator structure prepared by the method of forming a silicon-on-insulator structure according to any one of claims 1 to 7.

Description

Silicon-on-insulator structure and forming method thereof Technical Field The present invention relates to the field of semiconductor manufacturing, and more particularly, to a silicon-on-insulator structure and a method for forming the same. Background With the continuous development of integrated circuits and the continuous reduction of feature sizes of electronic components, finFET technology and SOI (Silicon-On-Insulator) technology, which are developed as a trigger, are two main routes at present. And as SOI technology continues to evolve, the demand for SOI structures is increasing. Typically, SOI structures are composed of a support substrate, an insulating layer, and a device layer, and the methods for fabricating SOI structures are currently mainly BESOI (bonding and backside etching techniques), SIMOX (separation by implanted oxygen) and Smartcut TM. The BESOI is used for corroding and removing the corrosion stopping layer on the device layer through different corrosion selection ratios of the corrosion stopping layer and the device layer to the corrosion solution, so that the thickness uniformity of the device layer can be effectively improved. Currently, the etch stop layer is mainly formed by heavily doped silicon or silicon germanium alloy such as boron, carbon, nitrogen, etc., wherein when the silicon germanium alloy is used as the etch stop layer, a mixed solution of HF, HNO 3 and Hac is required to be used for removing the silicon germanium alloy, and a porous layer of tens of nanometers is formed on the surface of the device layer in the process, and in order not to affect the related performance of the subsequent device, the porous layer needs to be removed effectively. This porous layer can be removed typically by a chemical mechanical polishing process, which makes the thickness uniformity of the device layer difficult to control, or by a mixed solution of HF and HNO 3, which can still make the micro-domain surface state of the device layer less than the requirements of the subsequent process. Disclosure of Invention The invention aims to provide a silicon-on-insulator structure and a forming method thereof, which can effectively repair a porous layer caused by removing an etching stop layer and improve the thickness uniformity of the surface of a device layer. In order to solve the above problems, a method for forming a silicon-on-insulator structure is provided, comprising the steps of: step S1, providing a first substrate and a second substrate, wherein the first substrate is provided with a first front surface and a first back surface which are oppositely arranged, an etching stop layer and a device layer are sequentially formed on the first front surface, and the second substrate is provided with a second front surface; Step S2, performing activation treatment on the surfaces of the second front surface and the device layer, and bonding the first substrate and the second substrate, wherein the second front surface faces the device layer; Step S3, thinning the first substrate from the first back surface, sequentially removing the rest of the first substrate and the etching stop layer through two selective etching processes to enable the surface of the device layer to be provided with a porous layer, and And S4, generating a sacrificial oxide layer on the device layer, filling and covering the porous layer by the sacrificial oxide layer, and removing the sacrificial oxide layer and the porous layer through a wet etching process to obtain the silicon-on-insulator structure. Optionally, step S1 includes: Providing a first substrate, wherein the first substrate is provided with a first front surface and a first back surface which are oppositely arranged; Forming an etch stop layer on the first front side; forming a device layer on the etch stop layer; Providing a second substrate, wherein a polysilicon capture layer is formed on the surface of the second substrate, and the surface of the polysilicon capture layer is the second front surface; forming an insulating layer by an oxidation process, and The insulating layer is located on the surface of the device layer, or the insulating layer comprises a first insulating layer and a second insulating layer, the first insulating layer is located on the surface of the device layer, and the second insulating layer is located on the second front surface. Further, step S2 includes: The second front surface and the surface of the insulating layer are activated by oxygen plasma when the insulating layer is positioned on the surface of the device layer, and And the second front surface faces the surface of the insulating layer and is subjected to low-temperature reinforcement treatment. Further, step S2 includes: The first insulating layer is positioned on the surface of the device layer, the surface of the first insulating layer and the surface of the second insulating layer are activated by oxygen plasma when the second insulating layer is positio