Search

CN-115513296-B - Semiconductor structure and forming method thereof

CN115513296BCN 115513296 BCN115513296 BCN 115513296BCN-115513296-B

Abstract

The structure comprises a substrate, a dielectric part and a second semiconductor material, wherein the dielectric part is embedded in the substrate, the second semiconductor material has lattice mismatch with the first semiconductor material, the second semiconductor material has two upper side walls and two lower side walls, the two upper side walls are in contact with the dielectric part, the two lower side walls are in contact with the substrate, the two lower side walls are not perpendicular to the top surface of the substrate, and the bottommost part of the dielectric part is lower than the topmost part of the two lower side walls. Embodiments of the present invention also relate to semiconductor structures and methods of forming the same.

Inventors

  • WU ZHENGXIAN
  • CHEN YISHENG

Assignees

  • 台湾积体电路制造股份有限公司

Dates

Publication Date
20260512
Application Date
20171208
Priority Date
20170914

Claims (20)

  1. 1. A semiconductor structure, comprising: a substrate comprising a first semiconductor material; A dielectric component embedded in the substrate; A second semiconductor material embedded in the substrate and disposed in a recess of the substrate, wherein the recess has a V-shaped V-groove surrounded by the substrate and a rectangular R-groove surrounded by the dielectric member in a cross-sectional view along a lateral direction of the recess, the second semiconductor material having a lattice mismatch with the first semiconductor material, the second semiconductor material having two upper side walls in contact with the dielectric member and defining the R-groove and two lower side walls in contact with the substrate and intersecting at an apex so as to define the V-groove, the two lower side walls being non-perpendicular to a top surface of the substrate, a bottommost portion of the dielectric member being lower than a topmost portion of the two lower side walls, wherein the side walls of the V-groove each form an angle of 45 ° to 59 ° with respect to a top surface of the substrate in a cross-sectional view along a lateral direction of the recess and in a cross-sectional view along a longitudinal direction of the recess; A plurality of fins formed of the second semiconductor material and located on the second semiconductor material disposed in the same recess, and A shallow trench isolation feature surrounding each of the plurality of fins, Wherein the shallow trench isolation feature and the dielectric feature surround a lower portion of the plurality of fins, and an upper portion of the plurality of fins protrudes from the shallow trench isolation feature and the dielectric feature, and wherein the dielectric feature extends from a top surface of the shallow trench isolation feature to a position below a bottom surface of the shallow trench isolation feature, and the shallow trench isolation feature is disposed within a lateral extent enclosed by the dielectric feature, the second semiconductor material including dislocations due to the lattice mismatch, the dislocations originating from sidewalls on one side of the V-groove and propagating in a direction substantially parallel to the top surface of the substrate and ending on sidewalls on the other side of the V-groove, wherein the dislocations are confined in the V-groove and do not propagate to the R-groove above, Wherein the semiconductor wafer in which the grooves are formed has a notch at an edge of the semiconductor wafer so as to represent a first crystal orientation of a [110] direction or a [100] direction, and wherein a longitudinal orientation of the grooves is parallel or perpendicular to the first crystal orientation, or an angle of 45 DEG or 135 DEG with respect to the first crystal orientation, Wherein the two upper side walls are non-perpendicular to the top surface of the substrate, and the two upper side walls are inclined toward the bottommost portions of the two lower side walls, Wherein in a top view the dielectric member surrounds the second semiconductor material under the plurality of fins from four sides and the dielectric member is further surrounded by the substrate, and wherein a top surface of the dielectric member is higher than and flush with a top surface of the second semiconductor material under the plurality of fins.
  2. 2. The semiconductor structure of claim 1, wherein the first semiconductor material comprises germanium and the second semiconductor material comprises indium arsenide.
  3. 3. The semiconductor structure of claim 2, wherein a bottommost portion of the dielectric component is lower than the bottommost portions of the two lower sidewalls.
  4. 4. The semiconductor structure of claim 1, wherein one of the two lower sidewalls comprises a hexagonal crystal plane.
  5. 5. The semiconductor structure of claim 1, wherein one of the two lower sidewalls comprises a (111) crystal plane defined by the first semiconductor material.
  6. 6. The semiconductor structure of claim 1, wherein a width of the R-slot in the lateral direction is less than a length in the longitudinal direction.
  7. 7. The semiconductor structure of claim 6, wherein the R-slot has a width in a range from 50nm to 1000 nm.
  8. 8. The semiconductor structure of claim 1, wherein the substrate is (001) silicon and the first crystal orientation is a <110> direction defined by the (001) silicon.
  9. 9. The semiconductor structure of claim 1, wherein a top width of the V-groove is at least a depth of the V-groove Multiple times.
  10. 10. The semiconductor structure of claim 9, wherein a top width of the V-groove is at least 50nm.
  11. 11. The semiconductor structure of claim 1, wherein the two lower sidewalls form an angle equal to or greater than 70.5 °.
  12. 12. The semiconductor structure of claim 1, wherein the second semiconductor material comprises indium.
  13. 13. A semiconductor structure, comprising: a substrate comprising a first semiconductor material, the substrate having a recess; A dielectric member surrounding the groove, wherein in a cross-sectional view along a lateral direction of the groove, the groove has a V-shaped V-groove surrounded by the substrate and a rectangular R-groove surrounded by the dielectric member, the V-groove having a first side wall and a second side wall, the first side wall intersecting the second side wall, wherein in a cross-sectional view along a lateral direction of the groove and in a cross-sectional view along a longitudinal direction of the groove, the side walls of the V-groove each form an angle of 45 ° to 59 ° with respect to a top surface of the substrate; A second semiconductor material disposed in the recess and in contact with the first semiconductor material, the second semiconductor material having a lattice mismatch with the first semiconductor material, dislocations in the second semiconductor material due to the lattice mismatch propagating from the first side walls to the second side walls of the V-groove in a direction parallel to the top surface of the substrate, wherein the dislocations are confined in the V-groove and do not propagate to the R-groove above; A plurality of fins formed of the second semiconductor material and located on the second semiconductor material disposed in the same recess, and A shallow trench isolation feature surrounding each of the plurality of fins, Wherein the shallow trench isolation member and the dielectric member surround lower portions of the plurality of fins, and upper portions of the plurality of fins protrude from the shallow trench isolation member and the dielectric member, and wherein the dielectric member extends from a top surface of the shallow trench isolation member to a position below a bottom surface of the shallow trench isolation member, and the shallow trench isolation member is disposed within a lateral range enclosed by the dielectric member, Wherein the second semiconductor material further has a third sidewall and a fourth sidewall in contact with the dielectric member, the third sidewall and the fourth sidewall being non-perpendicular to the top surface of the substrate, and the third sidewall and the fourth sidewall being inclined toward the bottommost portions of the first sidewall and the second sidewall, Wherein the semiconductor wafer in which the grooves are formed has a notch at an edge of the semiconductor wafer so as to represent a first crystal orientation of a [110] direction or a [100] direction, and wherein a longitudinal orientation of the grooves is parallel or perpendicular to the first crystal orientation, or an angle of 45 DEG or 135 DEG with respect to the first crystal orientation, Wherein in a top view the dielectric member surrounds the second semiconductor material under the plurality of fins from four sides and the dielectric member is further surrounded by the substrate, and wherein a top surface of the dielectric member is higher than and flush with a top surface of the second semiconductor material under the plurality of fins.
  14. 14. The semiconductor structure of claim 13, wherein the first semiconductor material is (001) silicon and the direction is a <110> crystal orientation defined by the (001) silicon.
  15. 15. The semiconductor structure of claim 14, wherein the first sidewall includes a (111) crystal plane defined by the (001) silicon.
  16. 16. The semiconductor structure of claim 13, wherein the first sidewall and the second sidewall intersect at an apex, thereby defining a V-groove between the first sidewall and the second sidewall, the V-groove having a top opening with a width, the apex having a distance to the top opening, the width being at least the distance Multiple times.
  17. 17. A method of forming a semiconductor structure, comprising: Receiving a semiconductor substrate; forming a first isolation member surrounding a portion of the semiconductor substrate; Recessing the portion of the semiconductor substrate to form an opening in the semiconductor substrate, the opening extending longitudinally in a first direction, a bottom of the opening surrounded by the semiconductor substrate having a V-shape in a plane perpendicular to the first direction such that the bottom of the opening forms a V-groove, and the opening further having a rectangular R-groove surrounded by the first isolation member, wherein in a cross-sectional view along the first direction and in a plane perpendicular to the first direction, sidewalls of the V-groove each form an angle of 45 ° to 59 ° with respect to a top surface of the semiconductor substrate; epitaxially growing a crystalline semiconductor material in the opening; patterning the crystalline semiconductor material to form a plurality of fins, each of the plurality of fins extending longitudinally in the first direction, wherein a top surface of the plurality of fins is flush with a top surface of the first isolation feature, and Forming a second isolation feature surrounding each of the plurality of fins, the second isolation feature being surrounded by the first isolation feature, wherein forming the second isolation feature further comprises recessing the first isolation feature and the second isolation feature such that a top surface of the plurality of fins is higher than a top surface of the recessed first isolation feature, Wherein the plurality of fins are disposed on the crystalline semiconductor material in the same V-groove, the crystalline semiconductor material including dislocations due to lattice mismatch, the dislocations originating from sidewalls on one side of the V-groove and propagating in a direction substantially parallel to a top surface of the substrate and terminating on sidewalls on the other side of the V-groove, wherein the dislocations are confined in the V-groove and do not propagate to the R-groove above, Wherein recessing the first and second spacer members comprises: recessing the second spacer using a first etching step of a first material composition, and Recessing the first spacer using a second etching step of a second material composition, wherein the first material composition is different from the second material composition, and both the recessed first spacer and recessed second spacer surround bottoms of the plurality of fins, while tops of the plurality of fins protrude from the recessed first spacer and recessed second spacer, and wherein the recessed first spacer extends from a top surface of the recessed second spacer to a position below a bottom surface of the recessed second spacer, and the recessed second spacer is disposed within a lateral extent enclosed by the recessed first spacer, Wherein epitaxially growing the crystalline semiconductor material in the opening comprises: heating the semiconductor substrate to a first temperature; Introducing a preflow gas at a second temperature; introducing a buffer precursor gas at a third temperature, and The epitaxial growth is continued at a fourth temperature, The relation between the first temperature and the fourth temperature is that the first temperature is greater than the second temperature, the fourth temperature is greater than the third temperature.
  18. 18. The method according to claim 17, wherein: the semiconductor substrate is a crystal structure defining a [110] direction, the [110] direction being along a top surface of the semiconductor substrate, and The first direction is parallel or perpendicular to the [110] direction.
  19. 19. The method of claim 17, wherein a bottommost portion of the first isolation component is lower than a bottommost portion of the opening.
  20. 20. The method of claim 17, wherein the crystalline semiconductor material comprises indium.

Description

Semiconductor structure and forming method thereof The application is a divisional application of an application patent application with the name of 'semiconductor structure and a forming method thereof' which is filed on the date of 2017, 12 and 08 and has the application number of 201711290808.8. Technical Field Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) generally increases while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. Such a downscaling process generally provides benefits by improving production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advances. Heterogeneous integration of different semiconductor materials (e.g., epitaxially grown III-V materials on silicon or silicon germanium substrates) has been introduced to improve the function and performance of Field Effect Transistors (FETs). However, the performance of devices fabricated using combinations of different semiconductor materials depends on the quality of the resulting structure. In particular, limiting dislocation defects is important in various semiconductor devices and processes because dislocation defects segment the monolithic crystal structure and cause undesirable and abrupt changes in electrical properties, which in turn result in poor material quality and limited performance. Accordingly, there is a need for a semiconductor structure and method that addresses these issues in order to enhance performance and reduce dislocation defects. Disclosure of Invention An embodiment of the invention provides a semiconductor structure comprising a substrate comprising a first semiconductor material, a dielectric component embedded in the substrate, and a second semiconductor material embedded in the substrate, the second semiconductor material having a lattice mismatch with the first semiconductor material, the second semiconductor material having two upper sidewalls in contact with the dielectric component and two lower sidewalls in contact with the substrate, the two lower sidewalls being non-perpendicular to a top surface of the substrate, a bottommost portion of the dielectric component being lower than a topmost portion of the two lower sidewalls. Another embodiment of the present invention provides a semiconductor structure comprising a substrate comprising a first semiconductor material having a recess with a bottom having a first sidewall and a second sidewall, the first sidewall intersecting the second sidewall, an isolation feature surrounding the recess, and a second semiconductor material disposed in the recess and in contact with the first semiconductor material, the second semiconductor material having a lattice mismatch with the first semiconductor material, dislocations in the second semiconductor material due to the lattice mismatch propagating from the first sidewall to the second sidewall in a direction parallel to a top surface of the substrate. Yet another embodiment of the present invention provides a method of forming a semiconductor structure including receiving a semiconductor substrate, forming a first isolation feature surrounding a portion of the semiconductor substrate, recessing the portion of the semiconductor substrate to form an opening in the semiconductor substrate, the opening extending longitudinally in a first direction, a bottom of the opening having a V-shape in a plane perpendicular to the first direction, epitaxially growing a crystalline semiconductor material in the opening, patterning the crystalline semiconductor material to form a plurality of fins, each of the plurality of fins extending longitudinally in the first direction, and forming a second isolation feature surrounding each of the plurality of fins, the second isolation feature being surrounded by the first isolation feature. Drawings The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1A, 1B, and 1C are diagrams showing three types of crystal orientations of silicon. Fig. 2A is a perspective view of a semiconductor structure h