CN-115527862-B - Thermally enhanced FCBGA package

Abstract

The present disclosure relates to thermally enhanced FCBGA packages. The semiconductor device has a heat spreader having an opening formed therethrough. A heat spreader is disposed over the substrate, wherein the semiconductor die is disposed in the opening over the substrate. A thermally conductive material, such as an adhesive or elastomeric plug, is disposed in the opening between the heat spreader and the semiconductor die. An electrically conductive layer is formed over the substrate, the heat spreader, and the thermally conductive material.

Inventors

• K.O. Kim
• W. Little Albert Bragenka
• D. S. Park

Assignees

• 星科金朋私人有限公司

Dates

Publication Date

20260505

Application Date

20220316

Priority Date

20210624

Claims (4)

1. 1. A method of manufacturing a semiconductor device, comprising: Providing a substrate; providing a heat spreader comprising an opening formed through the heat spreader, a half-etched portion formed around the opening at a first side of the heat spreader, and a top surface opposite the half-etched portion; Disposing a semiconductor die on the substrate; reflowing a plurality of solder bumps between the semiconductor die and a top surface of the substrate to mount the semiconductor die to the substrate; Disposing the heat spreader on the substrate, wherein the semiconductor die is located in the opening, wherein the half-etched portion creates a gap between the heat spreader and the substrate around the semiconductor die, wherein the heat spreader physically contacts a top surface of the substrate around the gap, and wherein the top surface of the heat spreader is coplanar with a back surface of the semiconductor die directly above the half-etched portion; Providing a thermally conductive material in the opening between the heat spreader and the semiconductor die, wherein the thermally conductive material is a preformed elastomeric plug, and wherein the preformed elastomeric plug includes an angled surface at a bottom of the preformed elastomeric plug prior to providing the preformed elastomeric plug in the opening, and The substrate and heat spreader are singulated together.
2. 2. The method of claim 1, further comprising forming an electrically conductive layer over the substrate, heat spreader, and thermally conductive material.
3. 3. The method of claim 1, further comprising disposing the thermally conductive material such that a surface of the thermally conductive material is substantially coplanar with a surface of the semiconductor die and a surface of the heat spreader.
4. 4. The method of claim 1, further comprising: providing a semiconductor package on the substrate, and The heat spreader is disposed on the semiconductor package.

Description

Thermally enhanced FCBGA package Technical Field The present invention relates generally to semiconductor fabrication and, more particularly, to a method and semiconductor device for forming a flip chip ball grid array package with enhanced thermal characteristics. Background Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide variety of functions such as signal processing, high speed computing, transmitting and receiving electromagnetic signals, controlling electronics, converting sunlight into electricity, and producing visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment. Semiconductor devices are typically manufactured using two complex manufacturing processes, front-end fabrication and back-end fabrication. Front end fabrication involves forming a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the relationship between voltage and current required to perform a circuit function. Back-end fabrication refers to dicing or singulating the completed wafer into individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along nonfunctional areas of the wafer known as streets or scribe lines. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to contact pads within the package. Electrical connections may be made with conductive layers, bumps, stud bumps, conductive paste, bond wires, or other suitable interconnect structures. An encapsulant or other molding compound is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system and the functionality of the semiconductor device is made available to other system components. Fig. 1a shows a semiconductor wafer 100 having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material. A plurality of semiconductor die or components 104 are formed on wafer 100 separated by passive, inter-die wafer regions or streets 106 as described above. The dicing streets 106 provide dicing areas to singulate the semiconductor wafer 100 into individual semiconductor die 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm). Fig. 1b shows a cross-sectional view of a portion of a semiconductor wafer 100. Each semiconductor die 104 has a back or passive surface 108 and an active surface 110, the active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within or on the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within active surface 110 to implement analog circuitry or digital circuitry, such as a Digital Signal Processor (DSP), ASIC, MEMS, memory, or other signal processing circuitry. Semiconductor die 104 may also contain Integrated Passive Devices (IPDs) for RF signal processing, such as inductors, capacitors, and resistors. The back surface 108 of the semiconductor wafer 100 may undergo an optional back grinding operation that utilizes a mechanical grinding or etching process to remove a portion of the base material 102 and reduce the thickness of the semiconductor wafer 100 and the semiconductor die 104. Conductive layer 112 is formed on active surface 110 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 112 may include one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 operates as a contact pad electrically connected to circuitry on the active surface 110. Conductive bump material is deposited on conductive layer 112 using an evaporation, electrolytic