CN-115543008-B - Current mirror circuit

Abstract

The present disclosure relates to a current mirror circuit. In one embodiment, an electronic device includes a first MOS type transistor and a second MOS type transistor connected as a current mirror, wherein the first transistor is diode-connected, and a first circuit configured to provide a first current equal to a first gate current of the first transistor multiplied by a size ratio of the first and second transistors.

Inventors

• R. Bolerstein

Assignees

• 意法半导体(格勒诺布尔2)公司

Dates

Publication Date

20260505

Application Date

20220630

Priority Date

20210630

Claims (20)

1. 1. An electronic device, comprising: A first transistor and a second transistor connected as a current mirror, wherein the first transistor is diode-connected, and A first circuit configured to provide a first current equal to a first gate current of the first transistor multiplied by a size ratio of the first transistor and the second transistor, Wherein the first circuit comprises K second circuits arranged in a cascaded manner, Where K is a relative integer number and, Wherein each second circuit is configured to isolate parasitic current from the previous circuit, and Wherein the second circuit of rank name i comprises an input node (Ai) connected to an output node of the second circuit of rank name i-1, a first output node (Bi) connected to an input node of the second circuit of rank name i+1, and a second output Node (NBi) connected to a second conductive terminal (S) of said second transistor (202), wherein i varies between 1 and K.
2. 2. The apparatus of claim 1, wherein the first circuit is connected to a first node that is interconnected with a first transistor gate of the first transistor and a second transistor gate of the second transistor, and wherein the first circuit is connected to a second node that is interconnected with a first conductive terminal of the first transistor and a first conductive terminal of the second transistor.
3. 3. The apparatus of claim 2, wherein the first circuit is configured to provide the first current to a second conductive terminal of the second transistor.
4. 4. The apparatus of claim 3, wherein the second node is configured to receive a supply voltage VDD.
5. 5. The apparatus of claim 1, wherein the first transistor and the second transistor are P-type MOS transistors.
6. 6. The apparatus of claim 1, wherein the first circuit comprises a first module configured to isolate the first gate current and a first current mirror.
7. 7. The apparatus of claim 6, wherein the first current mirror comprises a third transistor and a fourth transistor, the third transistor being diode-connected, and wherein second gate currents of the second transistor and the third transistor are negligible relative to the first gate current.
8. 8. The apparatus of claim 7, wherein the third transistor and the fourth transistor are P-type MOS transistors with a double oxide layer.
9. 9. The apparatus of claim 7, wherein a size ratio of the third transistor and the fourth transistor is equal to a size ratio of the first transistor and the second transistor.
10. 10. The apparatus of claim 6, wherein the first current mirror comprises a fifth transistor and a sixth transistor, the fifth transistor being diode-connected, and wherein a third gate current of the fifth transistor is proportional to the first gate current.
11. 11. The apparatus of claim 10, wherein the third gate current is equal to half the first gate current, and wherein a size ratio of the fifth transistor and the sixth transistor is equal to twice a size ratio of the first transistor and the second transistor.
12. 12. The apparatus of claim 1, wherein K is equal to 2.
13. 13. The apparatus of claim 1, wherein K is equal to 3.
14. 14. An electronic device, comprising: A first transistor and a second transistor connected as a current mirror, wherein the first transistor is diode-connected, and A first circuit configured to provide a first current equal to a first gate current of the first transistor multiplied by a size ratio of the first transistor and the second transistor, Wherein the first circuit comprises K second circuits arranged in a cascaded manner, Where K is a relative integer number and, Wherein each second circuit is configured to isolate parasitic current from the previous circuit, and Wherein each of the second circuits includes: a second current mirror including a seventh MOS transistor of the same size; a third current mirror including an eighth MOS transistor having a size ratio equal to that of the first transistor and the second transistor, and A second module configured to isolate parasitic current from another of the second circuits.
15. 15. The apparatus of claim 14, wherein the first circuit is connected to a first node that is interconnected with a first transistor gate of the first transistor and a second transistor gate of the second transistor, and wherein the first circuit is connected to a second node that is interconnected with a first conductive terminal of the first transistor and a first conductive terminal of the second transistor.
16. 16. The apparatus of claim 15, wherein the first circuit is configured to provide the first current to a second conductive terminal of the second transistor.
17. 17. The apparatus of claim 16, wherein the second node is configured to receive a supply voltage VDD.
18. 18. The apparatus of claim 14, wherein the first transistor and the second transistor are P-type MOS transistors.
19. 19. The apparatus of claim 14, wherein the second module is connected to an input node of a second circuit ranked between 1 and i-2 and an interconnection node of gates of the first transistor and the second transistor.
20. 20. The apparatus of claim 14, wherein the second current mirror and the third current mirror share the same ninth transistor, the ninth transistor being diode-connected.

Description

Current mirror circuit Cross reference to related applications The present application claims the benefit of French application number 2107030 filed on 30/6/2021, which is incorporated herein by reference. Technical Field The present invention relates generally to electronic circuits and systems. More particularly, the present invention relates to electronic circuits capable of reproducing current and, more particularly, to current mirror circuits. Background There are a variety of electronic circuits that are capable of performing basic operations used in more complex electronic devices. Among the most common basic operations to be performed, current mirrors are very useful. A current mirror circuit or current mirror is an electronic circuit that can replicate a current flowing through a first conductor into a second conductor. Disclosure of Invention Embodiments provide a current mirror circuit. Embodiments provide a current mirror circuit that can more accurately replicate current. Various embodiments address all or part of the disadvantages of known current mirror circuits. One embodiment provides an electronic device comprising a first MOS-type transistor and a second MOS-type transistor connected as a current mirror, the first transistor being diode-connected, and a first circuit adapted to provide a first current equal to a first gate current of the first transistor multiplied by a size ratio of the first and second transistors. According to one embodiment, the first circuit is connected to a first node and a second node, the first node is interconnected with the first and second transistor gates, the second node is interconnected with the first conductive terminal of the first transistor and the first conductive terminal of the second transistor, and the first circuit provides the first current to the second conductive terminal of the second transistor. According to one embodiment, the first and second transistors are P-type MOS transistors. According to one embodiment, the first circuit comprises a first module adapted to isolate the first gate current from the first current mirror. According to one embodiment, the first current mirror comprises a third and a fourth MOS transistor, the third transistor being diode connected, wherein the second gate current of the second and third transistor is negligible with respect to the first gate current. According to one embodiment, the third and fourth transistors are PMOS transistors with a double oxide layer. According to one embodiment, the size ratio of the third and fourth transistors is equal to the size ratio of the first and second transistors. According to one embodiment, the first current mirror comprises a fifth and a sixth transistor, the fifth transistor being diode connected, wherein a third gate current of the fifth transistor is proportional to the first gate current. According to one embodiment, the third gate current is equal to half the first gate current and the size ratio of the fifth and sixth transistors is equal to twice the size ratio of the first and second transistors. According to one embodiment, the first circuit comprises K second circuits arranged in a cascaded manner, wherein K is a relative integer, and each second circuit is adapted to isolate parasitic current from a previous circuit. According to one embodiment, K is equal to 2 or 3. According to one embodiment, the second circuit, named i (i varies between 1 and K), includes an input node connected to an output node of the second circuit, named i-1, a first output node connected to an input node of the second circuit, named i+1, and a second output node connected to a second conductive terminal of the second transistor. According to one embodiment, each second circuit comprises a second current mirror comprising seventh MOS transistors of the same size, a third current mirror comprising eighth MOS transistors of a size ratio equal to the size ratio of the first and second transistors, and a second module adapted to isolate parasitic current from another of the second circuits. According to one embodiment, the second module is connected to an input node of the second circuit, which is ranked between 1 and i-2, and to an interconnection node of the gates of the first and second transistors. According to one embodiment, the second and third current mirrors share the same ninth, diode-connected transistor. Drawings The above features and advantages and other features and advantages will be described in more detail in the following description of the particular embodiments, given by way of illustration, but not limited to the accompanying drawings, in which: FIG. 1 shows a current mirror circuit including a PMOS transistor; FIG. 2 schematically and partly shows an embodiment of an electronic device in block form; FIG. 3 shows the embodiment of FIG. 2 in more detail, schematically and partially in block form; FIG. 4 shows the embodiment of FIG. 2 in more detail, schematically a