CN-115549599-B - Transimpedance amplifier circuit applied to 50GPON

CN115549599BCN 115549599 BCN115549599 BCN 115549599BCN-115549599-B

Abstract

The invention discloses a transimpedance amplifier circuit applied to 50GPON, which mainly comprises a core amplifier, a burst switch capacitive coupling module, a single-ended-to-differential variable gain amplifier, an output driver, a first automatic gain control module, a second automatic gain control module, a differential mode offset elimination module, a differential amplifier and a direct-current voltage working point module, wherein a current signal is input from an IN end, is converted into a single-ended voltage signal through the core amplifier, is transmitted to the burst switch capacitive coupling module, is processed and output to obtain a signal with one end being boosted by direct-current voltage, and the other end is a signal voltage average value and is used as an input common mode level of the single-ended-to-differential variable gain amplifier. The single-ended to differential variable gain amplifier is used for converting single-ended signal voltage into differential voltage, and the output driver is used for transmitting the differential signal to the next chip and ensuring impedance matching in the transmission process.

Inventors

SHI JIAPENG
ZHANG HAO
DENG QING

Assignees

南京美辰微电子有限公司

Dates

Publication Date: 20260505
Application Date: 20220926

Claims (4)

1. The transimpedance amplifier circuit applied to 50GPON is characterized by comprising a CORE amplifier CORE_Amp, a burst switch capacitive coupling module burst cap, a single-ended-to-differential variable gain amplifier S2D_VGA, an output driver Drv, a first automatic gain control module AGC1, a second automatic gain control module AGC2, a differential mode offset cancellation module DOC, a differential amplifier AMP, a direct-current voltage operating point module Dummy, a resistor R_Dummy and a variable resistor Rf; The CORE amplifier core_amp is used for converting an input current signal into a single-ended voltage signal, the input end of the CORE amplifier core_amp is used for inputting the current signal and is connected with one end of the variable resistor Rf, and the output end of the CORE amplifier core_amp is connected with the other end of the variable resistor Rf; The direct-current voltage working point module Dummy is used for generating a direct-current voltage working point which is the same as the CORE amplifier CORE_Amp, the input end of the direct-current voltage working point module Dummy is connected with one end of a resistor R_Dummy, and the other end of the resistor R_Dummy is connected with the output end of the direct-current voltage working point module Dummy; the two input ends of the first automatic gain control module AGC1 are respectively connected with the output end of a CORE amplifier CORE_Amp and the output end of a direct-current voltage working point module Dummy, and the output end of the first automatic gain control module AGC1 is connected with the variable end of a variable resistor Rf; The output end of the CORE amplifier core_amp is connected with the input end of the burst switch capacitive coupling module burst cap, the two output ends of the burst switch capacitive coupling module burst cap are respectively connected with the two input ends of the single-ended-to-differential variable gain amplifier S2D_VGA, the two output ends of the single-ended-to-differential variable gain amplifier S2D_VGA are connected with the two input ends of the differential amplifier AMP, the two output ends of the differential amplifier AMP are connected with the two input ends of the output driver Drv, and the two output ends of the output driver Drv respectively output voltage signals V OUTP 、V OUTN ; Two input ends of the second automatic gain control module AGC2 are respectively connected with two output ends of the differential amplifier AMP, and the output end of the second automatic gain control module AGC2 is connected with the positive end of a power supply of the single-ended-to-differential variable gain amplifier S2D_VGA; The two input ends of the differential mode offset eliminating module DOC are respectively connected with the two output ends of the differential amplifier AMP, and the output end of the differential mode offset eliminating module DOC is connected with the power supply negative end of the single-ended-to-differential variable gain amplifier S2D_VGA.
2. The transimpedance amplifier circuit for 50GPON according to claim 1, wherein the first automatic gain control module AGC1 comprises a first resistor R1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first capacitor C1, a second capacitor C2, a switch TG1, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first current source I1, and a second current source I2; The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are PMOS transistors, and the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are NPN transistors; the switch TG1 is formed by parallelly connecting a PMOS tube, a second resistor R2 and NPMOS tubes, wherein a control signal RST is input to the grid electrode of the NPMOS tube, a control signal RSTB is input to the grid electrode of the PMOS tube, the control signal RSTB is a signal output by an inverter, the source electrode of the NPMOS tube, the source electrode of the PMOS tube and one end of the second resistor R2 are connected, and the drain electrode of the NPMOS tube, the drain electrode of the PMOS tube and the other end of the second resistor R2 are connected; The connection relation among each resistor, MOS tube, transistor and current source in the first AGC module AGC1 is as follows: One end of the first resistor R1 is connected with the output end of the CORE amplifier CORE_Amp, a core_out signal is input, the other end of the first resistor R1 is connected with the source electrode of the PMOS tube of the switch TG1, one end of the first capacitor C1 is connected with the drain electrode of the NMOS tube of the switch TG1 and the grid electrode of the third MOS tube M3, the other end of the first capacitor C1 is grounded, the drain electrode of the third MOS tube M3 is grounded, the source electrode of the third MOS tube is connected with one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected with the drain electrode of the first MOS tube M1 and the base electrode of the first transistor Q1, the grid electrode input voltage Vbp of the first MOS tube M1, the source electrode of the second MOS tube M2, the base electrode and the collector electrode of the third transistor Q3, the source electrode of the fifth MOS tube M5, the source electrode of the sixth MOS tube M6 and the positive electrode of the second current source I2; One end of a third resistor R3 is connected with the output end of the Dummy of the direct-current voltage working point module, a Dummy_out signal is input, the other end of the third resistor R3 is connected with the grid electrode of a fourth MOS transistor M4 and one end of a second capacitor C2, the other end of the second capacitor C2 is grounded, the drain electrode of the fourth MOS transistor M4 is grounded, the source electrode of the fourth MOS transistor M4 is connected with the drain electrode of the second MOS transistor M2 and the base electrode of a second transistor Q2, the cathode of a first current source I1 is grounded, the anode of the third current source I1 is connected with one end of a fifth resistor R5 and a sixth resistor R6, the other end of the fifth resistor R5 is connected with the emitter electrode of the first transistor Q1, the collector electrode of the first transistor Q1 is connected with the emitter electrode of the third transistor Q3, the other end of the sixth resistor R6 is connected with the emitter electrode of the second transistor Q2, the collector electrode of the second transistor Q2 is connected with the drain electrode of the fifth MOS transistor M5, the gate electrode of the fifth MOS transistor M5 is connected with the base electrode of the sixth MOS transistor Q2, the gate of the third transistor M6 is connected with the drain electrode of the fourth transistor Q6, the drain electrode of the third transistor Q2 is connected with the drain electrode of the third transistor Q2, the drain electrode of the third transistor Q7 is connected with the drain electrode of the third transistor Q2.
3. The transimpedance amplifier circuit for 50GPON according to claim 1, wherein the burst switched capacitive coupling module burst cap comprises a third capacitor C3, a fourth capacitor C4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a switch TG2, and a switch TG3; The switch TG2 and the switch TG3 are formed by connecting a NPMOS pipe and a PMOS pipe in parallel, the source electrode of the NPMOS pipe is connected with the source electrode of the PMOS pipe, the drain electrode of the NPMOS pipe is connected with the drain electrode of the PMOS pipe, the grid electrode of the NPMOS pipe is input with a control signal RST, the grid electrode of the PMOS pipe is input with a control signal RSTB, the control signal RSTB is a signal output by an inverter, the control signal RST respectively controls the switch TG2 and the switch TG3 after passing through the inverter, and if sudden common mode level changes, the switch TG2 and the switch TG3 are started under the action of the control signal RST; The connection relation among each resistor, capacitor and switch in the burst capacitor coupling module burst cap is as follows: One end of the third capacitor C3 is input with a voltage Vip, the other end of the third capacitor C3 is connected with one ends of the eighth resistor R8 and the ninth resistor R9, and is used as an output end of the burst switch capacitive coupling module burst cap to output a voltage signal Vop, one end of the fourth capacitor C4 is grounded, and the other end of the fourth capacitor C4 is connected with one ends of the tenth resistor R10 and the eleventh resistor R11, and is used as an output end of the burst switch capacitive coupling module burst cap to output a voltage signal Von; The other end of the ninth resistor R9 is connected with the source electrode of the NPMOS pipe of the switch TG2, the other end of the eleventh resistor R11 is connected with the source electrode of the NPMOS pipe of the switch TG3, the other ends of the eighth resistor R8 and the tenth resistor R10, and the drain electrodes of the NPMOS pipes of the switch TG2 and the switch TG3 are connected, and the static voltage VCM is input.
4. The transimpedance amplifier circuit according to claim 1, wherein the second automatic gain control module AGC2 comprises a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteen resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, a switch TG4, and a differential amplifier OP1; The seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9, and the tenth MOS transistor M10 are PMOS transistors, and the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, the tenth transistor Q10, the eleventh transistor Q11, and the twelfth transistor Q12 are NPN transistors; The switch TG4 is formed by connecting a NPMOS pipe and a PMOS pipe in parallel, the source electrode of the NPMOS pipe is connected with the source electrode of the PMOS pipe, the drain electrode of the NPMOS pipe is connected with the drain electrode of the PMOS pipe, the grid electrode of the NPMOS pipe is input with a control signal RST, the grid electrode of the PMOS pipe is input with a control signal RSTB, and the control signal RSTB is a signal output by an inverter; One end of a twelfth resistor R12 is input with a voltage Vip and is connected with the base electrode of a fifth transistor Q5, the other end of the twelfth resistor R12 is connected with one end of a thirteenth resistor R13 and the base electrode of a seventh transistor Q7, the other end of the thirteenth resistor R13 is input with a voltage Vin and is connected with the base electrode of a sixth transistor Q6, the emitter electrode of the fifth transistor Q5 and the collector electrode of an eleventh transistor Q11 are connected, the collector electrode of the sixth transistor Q6 is connected with the emitter electrode of a ninth transistor Q9, the collector electrode of the fifth transistor Q5 is connected with the emitter electrode of an eighth transistor Q8, the base electrode and the collector electrode of the eighth transistor Q9, the base electrode and the collector electrode of the tenth transistor Q10, the source electrode of the ninth transistor M9 and the source electrode of the tenth MOS transistor M10; The base electrode of the eleventh transistor Q11 inputs a voltage signal Vbn, the emitter electrode of the eleventh transistor is connected to one ends of a fourteenth resistor R14 and a fifteenth resistor R15, the other end of the fifteenth resistor R15 is connected to the source electrode of the NPMOS pipe of the switch TG4, the drain electrode of the NPMOS pipe of the switch TG4, the other end of the fourteenth resistor R14, a sixteenth resistor R16, a fifth capacitor C5, a sixth capacitor C6, one end of a seventh capacitor C7, the drain electrode of the seventh MOS pipe M7, and the drain electrode of the eighth MOS pipe M8 are connected to the ground; The base electrode of the twelfth transistor Q12 inputs a voltage signal Vbn, the emitter of the twelfth transistor Q12 is connected with the other end of the sixteenth resistor R16, the collector of the twelfth transistor Q12 is connected with the emitter of the seventh transistor Q7, one end of the seventeenth resistor R17 and the other end of the fifth capacitor C5, the other end of the seventeenth resistor R17 is connected with the grid electrode of the seventh MOS transistor M7, the collector of the seventh transistor Q7 is connected with the emitter of the tenth transistor Q10, the collector of the eleventh transistor Q11, the other end of the sixth capacitor C6 and one end of the eighteenth resistor R18 are connected, and the other end of the eighteenth resistor R18 is connected with the grid electrode of the eighth MOS transistor M8; The drain of the ninth MOS transistor M9 is connected to the source of the seventh MOS transistor M7 and the positive input terminal of the differential amplifier OP1, the drain of the tenth MOS transistor M10 is connected to one end of the nineteenth resistor R19 and the negative input terminal of the differential amplifier OP1, the other end of the nineteenth resistor R19 is connected to the source of the eighth MOS transistor M8, and the output terminal of the differential amplifier OP1 serves as the output terminal of the second automatic gain control module AGC2 to output the voltage signal Vagc2.

Description

Transimpedance amplifier circuit applied to 50GPON Technical Field The invention relates to the technical field of microelectronics, in particular to a transimpedance amplifier circuit applied to 50 GPON. Background The demands of large bandwidth, low jitter VR service, ultra-low time delay and high reliability industrial park service promote the evolution of PON technology from GPON to 10G PON and then to next generation 50G PON, and the development is continued towards the directions of improving service bandwidth, enhancing full-service intelligent bearing and operation and maintenance capability. From the aspect of demand, the comprehensive bearing demand of the multi-scenario is oriented, the 50G PON has obvious improvement in key characteristics such as line bandwidth, low time delay, channeling capability and the like, and the evolution upgrading of an industrial park from PON 1.0 (equipment interconnection) to PON2.0 (data intercommunication) to PON 3.0 (industrial intelligence) is greatly promoted. From the standard level, the current standardization generally enters the Amd1 formulation stage, the general framework requirement of the next-generation PON is defined, the framework of the single-wavelength TDM-PON is determined, the coexistence and evolution of XG (S) -PON are required to be supported, and the uplink and downlink symmetrical 50G rate is determined. As a front-end chip for converting photocurrent into differential voltage, a transimpedance amplifier (TIA) chip plays a crucial role in link performance, and in 50GPON system application, a fast burst response time is required for the TIA, linearity in a dynamic range is high, equivalent input noise is low, and architecture design based on these core indexes TIA becomes particularly difficult. Disclosure of Invention The invention aims to provide a transimpedance amplifier circuit applied to 50GPON, which realizes quick establishment of common-mode voltage and quick switching of gain. In order to achieve the functions, the invention designs a transimpedance amplifier circuit applied to 50GPON, wherein the transimpedance amplifier comprises a CORE amplifier CORE_Amp, a burst switch capacitive coupling module burst cap, a single-ended to differential variable gain amplifier S2D_VGA, an output driver Drv, a first automatic gain control module AGC1, a second automatic gain control module AGC2, a differential mode offset elimination module DOC, a differential amplifier AMP, a direct-current voltage working point module Dummy, a resistor R_Dummy and a variable resistor Rf; The CORE amplifier core_amp is used for converting an input current signal into a single-ended voltage signal, the input end of the CORE amplifier core_amp is used for inputting the current signal and is connected with one end of the variable resistor Rf, and the output end of the CORE amplifier core_amp is connected with the other end of the variable resistor Rf; The direct-current voltage working point module Dummy is used for generating a direct-current voltage working point which is the same as the CORE amplifier CORE_Amp, the input end of the direct-current voltage working point module Dummy is connected with one end of a resistor R_Dummy, and the other end of the resistor R_Dummy is connected with the output end of the direct-current voltage working point module Dummy; the two input ends of the first automatic gain control module AGC1 are respectively connected with the output end of a CORE amplifier CORE_Amp and the output end of a direct-current voltage working point module Dummy, and the output end of the first automatic gain control module AGC1 is connected with the variable end of a variable resistor Rf; The output end of the CORE amplifier core_amp is connected with the input end of the burst switch capacitive coupling module burst cap, the two output ends of the burst switch capacitive coupling module burst cap are respectively connected with the two input ends of the single-ended-to-differential variable gain amplifier S2D_VGA, the two output ends of the single-ended-to-differential variable gain amplifier S2D_VGA are connected with the two input ends of the differential amplifier AMP, the two output ends of the differential amplifier AMP are connected with the two input ends of the output driver Drv, and the two output ends of the output driver Drv respectively output voltage signals V OUTP、VOUTN; Two input ends of the second automatic gain control module AGC2 are respectively connected with two output ends of the differential amplifier AMP, and the output end of the second automatic gain control module AGC2 is connected with the positive end of a power supply of the single-ended-to-differential variable gain amplifier S2D_VGA; The two input ends of the differential mode offset eliminating module DOC are respectively connected with the two output ends of the differential amplifier AMP, and the output end of the differential mode offset eliminating module DOC is