CN-115587026-B - Chip testing method and device, storage medium and chip

CN115587026BCN 115587026 BCN115587026 BCN 115587026BCN-115587026-B

Abstract

The embodiment of the application discloses a chip testing method, a device, a storage medium and a chip, and relates to the field of chips. In addition, the test data generated by the chip is stored by the external memory, and the test data is actively collected on the IO pins of the chip relative to the test equipment, so that the IO operation of the chip can be reduced, and the processing cost of the chip is reduced.

Inventors

YANG JIANMING
HUANG LIWEI
LIU HAO
ZHANG JING

Assignees

珠海泰芯半导体有限公司

Dates

Publication Date: 20260508
Application Date: 20220927

Claims (7)

1. The chip testing method is characterized in that the chip is provided with a first debugging pin and a second debugging pin, the first debugging pin and the second debugging pin are IO pins, the first debugging pin is connected with a clock pin of an off-chip memory, and the second debugging pin is connected with a data pin of the off-chip memory; Wherein the method comprises the following steps: When the preset condition is met, switching to a test mode; in a test mode, receiving a clock signal through the first debug pin; receiving a test instruction from test equipment through the second debugging pin; Executing test operation according to the test instruction; The test instruction comprises, but is not limited to, a register reading instruction, a register writing instruction, an on-chip memory reading instruction, an on-chip memory writing instruction, a program continuous execution instruction and a program starting address setting instruction, a main program code and an associated cyclic check CRC code in a main code area are read according to the on-chip memory reading instruction, the CRC code is calculated according to the read main program code, whether the read CRC code and the calculated CRC code are identical or not is compared, if the read CRC code and the calculated CRC code are identical, the main program code is checked to be passed, if the main program code and the main program code are not checked to be passed, and communication is carried out between the chip and the off-chip memory through a serial peripheral interface SPI protocol.
2. The method of claim 1, wherein the preset condition comprises receiving a switch instruction from a user, or receiving a specified sequence from a test device through a second debug pin, or detecting that the levels on the first debug pin and the second debug pin are high.
3. The method of claim 2, wherein the clock signal is provided by a test device or an external clock source.
4. A method according to claim 3, wherein the chip is an STM32 series chip.
5. The chip testing device is characterized in that the chip is provided with a first debugging pin and a second debugging pin, the first debugging pin and the second debugging pin are IO pins, the first debugging pin is connected with a clock pin of an off-chip memory, and the second debugging pin is connected with a data pin of the off-chip memory; Wherein, the chip testing device includes: the switching unit is used for switching to a test mode when a preset condition is met; The receiving and transmitting unit is used for receiving a clock signal through the first debugging pin in a test mode; The receiving and transmitting unit is further configured to receive a test instruction from a test device through the second debug pin; The execution unit is used for executing test operation according to the test instruction; And the test instruction comprises, but is not limited to, a read register instruction, a write register instruction, a read on-chip memory instruction, a write on-chip memory instruction, a program continuous execution instruction and a program start address setting instruction, reads a main program code and an associated cyclic check CRC code in a main code area according to the read on-chip memory instruction, calculates the CRC code according to the read main program code, compares whether the read CRC code and the calculated CRC code are identical, if so, the main program code passes the check, if not, the main program code does not pass the check, and the chip and the off-chip memory communicate through a serial peripheral interface SPI protocol.
6. A computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the chip test method according to any one of claims 1 to 4.
7. A chip comprising a processor and a memory, wherein the memory stores a computer program adapted to be loaded by the processor and to perform the chip testing method according to any one of claims 1-4.

Description

Chip testing method and device, storage medium and chip Technical Field The present application relates to the field of chips, and in particular, to a chip testing method, a device, a storage medium, and a chip. Background The chip may perform FT (FINAL TEST ) before mass production, and for cost reasons, the same core die may use different packaging modes, and the number of IO pins of the chips in different packaging modes may also be different. In the existing FT, the test equipment can communicate with each IO pin of the chip to complete the test process, however, when the chips in different packaging modes are tested, the test equipment and test codes in the chips are required to be configured according to the IO pin distribution condition of the chips, so that the writing workload of the test codes can be greatly increased, and the test efficiency is low. Disclosure of Invention The embodiment of the application provides a chip testing method, a device, a storage medium and a chip, which can solve the problem that test equipment in the prior art writes test codes for chips in different packaging modes during testing and has low test efficiency. The technical scheme is as follows: In a first aspect, an embodiment of the present application provides a method for testing a chip, where the chip is provided with a first debug pin and a second debug pin, where the first debug pin and the second debug pin are IO pins, the first debug pin is connected to a clock pin of an off-chip memory, and the second debug pin is connected to a data pin of the off-chip memory; Wherein the method comprises the following steps: When the preset condition is met, switching to a test mode; in a test mode, receiving a clock signal through the first debug pin; receiving a test instruction from test equipment through the second debugging pin; Executing test operation according to the test instruction; And if the test operation generates test data, writing the test data into an off-chip memory through the second debugging pin. In a second aspect, an embodiment of the present application provides a chip testing device, which is applied to a chip, where the chip is provided with a first debug pin and a second debug pin, the first debug pin and the second debug pin are IO pins, the first debug pin is connected to a clock pin of an off-chip memory, and the second debug pin is connected to a data pin of the off-chip memory; Wherein, the chip testing device includes: the switching unit is used for switching to a test mode when a preset condition is met; The receiving and transmitting unit is used for receiving a clock signal through the first debugging pin in a test mode; The receiving and transmitting unit is further configured to receive a test instruction from a test device through the second debug pin; The execution unit is used for executing test operation according to the test instruction; And the writing unit is used for writing the test data into the off-chip memory through the second debugging pin if the test operation generates the test data. In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the above-described method steps. In a fourth aspect, embodiments of the present application provide a chip, which may include a processor and a memory, wherein the memory stores a computer program adapted to be loaded by the processor and to perform the above-described method steps. The technical scheme provided by the embodiments of the application has the beneficial effects that at least: The chip performs a test operation based on the test instruction from the test device, and then writes test data generated in the test process into an external memory so that the test device reads the test data in the external memory to judge whether the test is passed or not. Therefore, when the test equipment tests the chips with the same core in different packaging modes, the test equipment and the programs in the chips are not required to be changed, the chips with different packaging modes can be tested by using the same set of programs, the compatibility of the test process is improved, the writing workload of test codes is reduced, in addition, the test data generated by the chips are stored by the external memory, and the test data are actively collected on IO pins of the chips relative to the test equipment, so that IO operation of the chips can be reduced, and the processing cost of the chips is reduced. Drawings In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings witho