CN-115588640-B - Semiconductor alignment structure and manufacturing method thereof

Abstract

A manufacturing method of an alignment structure comprises the steps of providing a substrate and a plurality of conductive features, wherein the conductive features are arranged on the substrate at intervals, conformally depositing a first stacking layer on the substrate and the conductive features, wherein the first stacking layer is provided with a plurality of concave parts, forming a sacrificial layer on the first stacking layer, removing part of the sacrificial layer to form a plurality of covers respectively located on the concave parts, performing anisotropic etching on the first stacking layer by taking the covers as etching masks to form a plurality of first stacking parts and expose the conductive features, conformally depositing a second stacking layer on the first stacking parts and the conductive features, and performing etching lithography on the second stacking layer to form a plurality of second stacking parts respectively located on the first stacking parts and a plurality of alignment through holes respectively exposing the conductive features. Therefore, the semiconductor element can be placed on the conductive feature by utilizing the alignment through hole accurately, so that the semiconductor element is in contact with and electrically connected with the conductive feature.

Inventors

• LAI CHAOWEN
• GONG YAOXIONG

Assignees

• 南亚科技股份有限公司

Dates

Publication Date

20260512

Application Date

20210930

Priority Date

20210705

Claims (10)

1. 1. A method for manufacturing a semiconductor alignment structure, comprising: providing a substrate and a plurality of conductive features, wherein the conductive features are arranged on the substrate at intervals; conformally depositing a first stacked layer on the substrate and the conductive features, wherein the first stacked layer has a plurality of recesses thereon; forming a sacrificial layer on the first stacked layer, and removing part of the sacrificial layer to form a plurality of covers respectively located in the plurality of concave parts; performing anisotropic etching process on the first stacked layer by using the covers as etching masks, so as to expose the conductive features and form a plurality of first stacked portions; Conformally depositing a second stacked layer over the first stacked portions and the conductive features, and And performing etching lithography on the second stacked layer to form a plurality of second stacked portions and a plurality of alignment through holes, wherein the second stacked portions are respectively located above the first stacked portions, and the alignment through holes respectively expose the conductive features.
2. 2. The method of manufacturing according to claim 1, characterized by further comprising: Before forming the alignment through holes, a dielectric layer is formed on the second stacked layer, wherein the alignment through holes also penetrate through the dielectric layer.
3. 3. The method of claim 1, wherein the masking is selectively removed prior to forming the second stack layer over the first stacks and the conductive features.
4. 4. The method of manufacturing according to claim 1, wherein the thickness of the first stacked layer is greater than the thickness of the second stacked layer.
5. 5. The method of claim 1, wherein the second stacked layer is formed by an atomic layer deposition process.
6. 6. The method of claim 1, wherein the top ends of the second stacks are higher than the top ends of the conductive features.
7. 7. The method of claim 1, wherein the first stacking portions or the second stacking portions have a concave top.
8. 8. The method of claim 1, wherein the conductive features have a width of less than or equal to 40 nm.
9. 9. The method of claim 1, further comprising forming a plurality of dielectric upper portions over the second stacks, respectively.
10. 10. The method of claim 9, wherein a ratio of a height difference between the dielectric upper portions and the adjacent conductive features to a width of the conductive features is between 30 and 35.

Description

Semiconductor alignment structure and manufacturing method thereof Technical Field The present invention relates to alignment structures and methods for fabricating the same, and more particularly to alignment structures for semiconductor processes and methods for fabricating the same. Background With the advancement and development of technology, electronic devices are becoming smaller in size and have higher requirements for various performances. Accordingly, various components (e.g., capacitors and conductive lines) in semiconductor structures must be scaled down to meet various requirements. However, as semiconductor devices shrink, it becomes difficult to precisely align and connect the various devices, which can seriously affect the various properties of the semiconductor structure and even render it inoperable. This is especially true in semiconductor structures of smaller dimensions. Accordingly, many civil enterprises and related research units in the semiconductor industry have invested a great deal of money, manpower and time to study, and there is a need to improve such conditions. Disclosure of Invention An objective of the present invention is to provide a method for manufacturing a semiconductor alignment structure capable of solving the above-mentioned problems, which comprises providing a substrate and a plurality of conductive features, wherein the plurality of conductive features are arranged on the substrate at intervals, conformally depositing a first stacked layer on the substrate and the plurality of conductive features, wherein the first stacked layer has a plurality of recesses thereon, forming a sacrificial layer on the first stacked layer, removing a portion of the sacrificial layer to form a plurality of masks on the recesses, performing an anisotropic etching process on the first stacked layer with the plurality of masks as an etching mask to form a plurality of first stacked portions, thereby exposing the plurality of conductive features, conformally depositing a second stacked layer on the plurality of first stacked portions and the plurality of conductive features, and performing an etching lithography process on the second stacked layer, thereby forming a plurality of second stacked portions and a plurality of alignment vias, wherein the plurality of second stacked portions are respectively located above the plurality of first stacked portions, and the plurality of alignment vias are respectively exposed by the plurality of conductive features. In one or more embodiments of the present invention, the method further includes forming a dielectric layer on the second stacked layer prior to forming the plurality of alignment vias, wherein the plurality of alignment vias are formed through the dielectric layer. In one or more embodiments of the present invention, the masking is selectively removed prior to forming the second stack layer over the plurality of first stacks and the plurality of conductive features. In one or more embodiments of the invention, the thickness of the first stacked layer is greater than the thickness of the second stacked layer. In one or more embodiments of the invention, the second stacked layer is formed by an atomic layer deposition process. Another objective of the present invention is to provide a semiconductor alignment structure including a substrate, a plurality of conductive features and a plurality of stacked structures. The plurality of stacked structures and the plurality of conductive features are alternately arranged on the substrate, each of the plurality of stacked structures having a first stacked portion and a second stacked portion above the first stacked portion, wherein a height of the plurality of stacked structures is greater than a height of the plurality of conductive features. In one or more embodiments of the invention, the first stack portion or the second stack portion has a concave top. In one or more embodiments of the invention, the width of the conductive features is less than or equal to 40nm. In one or more embodiments of the invention, the stacked structure further includes a dielectric upper portion disposed above the stacked structure. In one or more embodiments of the invention, the ratio of the difference in height of the stacked structure and adjacent conductive features to the width of the conductive features is approximately between 30 and 35. In summary, the present invention provides an alignment structure for a semiconductor device and a method for fabricating the same, which can precisely utilize the alignment via to place the semiconductor device on the conductive feature, so that the semiconductor device is in contact with and electrically connected to the conductive feature. Therefore, the semiconductor elements with small size can be prevented from being connected with each other accurately due to the process problem, and further the occurrence of short circuit or even the situation that the semiconduct