CN-115588661-B - Semiconductor structure and method for forming capacitor structure

CN115588661BCN 115588661 BCN115588661 BCN 115588661BCN-115588661-B

Abstract

The embodiment of the disclosure provides a semiconductor structure and a method for forming a capacitor structure, the method comprises the steps of providing a first substrate, sequentially comprising a bottom supporting layer, a first sacrificial layer and a mask layer, wherein the first sacrificial layer is provided with a lower electrode penetrating through the bottom supporting layer, the surface of the lower electrode is flush with the mask layer and is connected with a capacitor contact pad in the bottom supporting layer, etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer, and forming an intermediate supporting layer and a top supporting layer on the second sacrificial layer to form the capacitor structure.

Inventors

LIU TAO
XIA JUN
Zhan Kangshu
LI SEN
XU PENGHUI
WAN QIANG

Assignees

长鑫存储技术有限公司

Dates

Publication Date: 20260512
Application Date: 20221028

Claims (14)

1. A method of forming a capacitor structure, the method comprising: The method comprises the steps of providing a first substrate, wherein the first substrate sequentially comprises a bottom supporting layer, a first sacrificial layer and a mask layer, wherein the first sacrificial layer is provided with a lower electrode penetrating through the mask layer, and the surface of the lower electrode is flush with the mask layer and connected with a capacitor contact pad in the bottom supporting layer; etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer; An intermediate support layer and a top support layer are formed on the second sacrificial layer to form a capacitor structure.
2. The method of forming of claim 1, wherein providing a first substrate comprises: Providing a second substrate, wherein the second substrate sequentially comprises a bottom supporting layer, an initial first sacrificial layer and an initial mask layer; Etching the initial mask layer and the initial first sacrificial layer with a first pattern identical to the capacitor hole pattern to form a mask layer and a first sacrificial layer with capacitor holes; and after depositing electrode materials in the capacitor holes, forming the lower electrode.
3. The method of forming of claim 2, wherein etching the initial mask layer and the initial first sacrificial layer in a first pattern identical to the pattern of capacitive holes to form a mask layer and a first sacrificial layer having capacitive holes, comprises: etching the initial mask layer with a first pattern identical to the capacitor hole pattern to form a mask layer with the first pattern; And etching the initial first sacrificial layer by using the mask layer with the first pattern to form a first sacrificial layer with the capacitor hole.
4. The method of forming of claim 3, wherein etching the initial mask layer in a first pattern identical to the capacitor hole pattern to form a mask layer having the first pattern, comprises: forming a composite mask layer with a second pattern on the initial mask layer; and patterning the initial mask layer based on the composite mask layer with the second pattern to form a mask layer with the first pattern.
5. The method of forming of claim 3, wherein etching the initial first sacrificial layer with the mask layer having the first pattern to form the first sacrificial layer having the capacitor hole comprises: Forming a first electrode in the aperture of the first pattern, the first electrode being flush with the mask layer; And etching the initial first sacrificial layer by adopting a metal auxiliary chemical etching process to form a first sacrificial layer with the capacitance hole, wherein the first electrode is connected with the capacitance contact pad to form a second electrode along with consumption of the initial first sacrificial layer.
6. The method of forming of claim 5, wherein forming a first electrode in the aperture of the first pattern flush with the mask layer comprises: Depositing the electrode material in the pores of the first pattern to form an initial first electrode; and etching the initial first electrode by adopting a dry etching process, a wet etching process or a chemical mechanical polishing process to form the first electrode which is flush with the mask layer.
7. The method of forming of claim 6, wherein forming the lower electrode after depositing electrode material in the capacitor hole after forming the second electrode comprises: Depositing the electrode material in the capacitor hole after the second electrode is formed; And removing redundant electrode materials by adopting the dry etching process, the wet etching process or the chemical mechanical polishing process to form a lower electrode which is flush with the mask layer.
8. The method of any one of claims 1 to 7, wherein etching the first sacrificial layer to a predetermined first thickness to form a second sacrificial layer comprises: Removing the mask layer by adopting a dry etching process or a wet etching process; and etching the first sacrificial layer by adopting a dry etching process or a wet etching process to form the second sacrificial layer with the first preset thickness.
9. The forming method according to claim 8, wherein forming an intermediate support layer on the second sacrificial layer includes: Covering an intermediate support material layer on the second sacrificial layer and the lower electrode; Forming a spin-on hard mask layer on the middle support material layer; and simultaneously removing the middle supporting material layer and the spin-on hard mask layer on the top and the side wall of the lower electrode to form the middle supporting layer.
10. The forming method according to any one of claims 1 to 7, characterized in that forming an intermediate support layer and a top support layer on the second sacrificial layer to form a capacitor structure, comprising: Forming a third sacrificial layer on the intermediate support layer, wherein a top surface of the third sacrificial layer is lower than a top surface of the lower electrode; forming the top support layer on the third sacrificial layer; patterning the top support layer, forming a first opening in the top support layer, and removing the second sacrificial layer and the third sacrificial layer through the first opening; and sequentially forming a dielectric layer and an upper electrode on the lower electrode to obtain the capacitor structure.
11. The method of forming of claim 10, wherein the second sacrificial layer is a different material than the third sacrificial layer; the material of the third sacrificial layer is oxide.
12. The forming method according to claim 10, wherein forming a third sacrificial layer on the intermediate support layer includes: forming an initial third sacrificial material layer on the intermediate support layer, wherein a top surface of the initial third sacrificial material layer is higher than a top surface of the lower electrode; removing part of the initial third sacrificial material layer by adopting a chemical mechanical polishing process to form an initial third sacrificial layer which is flush with the top surface of the lower electrode; And etching the initial third sacrificial layer by adopting a dry etching process or a wet etching process to form a third sacrificial layer lower than the top surface of the lower electrode.
13. The method of forming of claim 10, wherein patterning the top support layer, forming a first opening in the top support layer, removing the second sacrificial layer and the third sacrificial layer via the first opening, comprises: Etching the top support layer, the middle support layer, the second sacrificial layer and the third sacrificial layer between any adjacent lower electrodes to form the first opening; and etching the second sacrificial layer and the third sacrificial layer through the first opening by adopting a wet etching process.
14. A semiconductor structure comprising a capacitor structure formed by the method of any one of claims 1 to 13.

Description

Semiconductor structure and method for forming capacitor structure Technical Field The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method of forming a capacitor structure. Background A dynamic random access memory (Dynamic Random Access Memory, DRAM) includes a transistor and capacitor structure. In order to increase the capacitance of the capacitor structure, the capacitor often has a high aspect ratio, which requires a structure of two sacrificial layers and three supporting layers to realize the effect of stabilizing the capacitor structure during the design of the capacitor structure. However, the current technology has difficulty in satisfying the smoothness of the vertical and side walls of the capacitor profile and is liable to affect the stability of the capacitor structure. Disclosure of Invention The embodiment of the disclosure provides a semiconductor structure and a method for forming a capacitor structure. In a first aspect, an embodiment of the disclosure provides a method for forming a capacitor structure, which includes providing a first substrate, wherein the first substrate sequentially includes a bottom support layer, a first sacrificial layer with a lower electrode penetrating through the bottom support layer, and a mask layer, wherein the surface of the lower electrode is flush with the mask layer and is connected with a capacitor contact pad in the bottom support layer, etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer, and forming an intermediate support layer and a top support layer on the second sacrificial layer to form the capacitor structure. In some embodiments, the method comprises providing a second substrate, wherein the second substrate comprises the bottom support layer, an initial first sacrificial layer and an initial mask layer in sequence, etching the initial mask layer and the initial first sacrificial layer in the same first pattern as the capacitor hole pattern to form a mask layer and a first sacrificial layer with capacitor holes, and forming the lower electrode after depositing electrode materials in the capacitor holes. In some embodiments, etching the initial mask layer and the initial first sacrificial layer in the same first pattern as the capacitor hole pattern to form a mask layer and a first sacrificial layer having a capacitor hole includes etching the initial mask layer in the same first pattern as the capacitor hole pattern to form a mask layer having a first pattern, and etching the initial first sacrificial layer in the mask layer having the first pattern to form a first sacrificial layer having the capacitor hole. In some embodiments, etching the initial mask layer with a first pattern identical to the capacitor hole pattern to form a mask layer with the first pattern includes forming a composite mask layer with a second pattern on the initial mask layer, and patterning the initial mask layer based on the composite mask layer with the second pattern to form a mask layer with the first pattern. In some embodiments, the initial first sacrificial layer is etched with the mask layer with the first pattern to form a first sacrificial layer with the capacitor hole, and the first sacrificial layer is etched with a metal-assisted chemical etching process to form a first sacrificial layer with the capacitor hole, wherein the first electrode is connected with the capacitor contact pad to form a second electrode as the initial first sacrificial layer is consumed. In some embodiments, forming a first electrode flush with the mask layer in the aperture of the first pattern includes depositing the electrode material in the aperture of the first pattern to form an initial first electrode, and etching the initial first electrode using a dry etching process, a wet etching process, or a chemical mechanical polishing process to form the first electrode flush with the mask layer. In some embodiments, after forming the second electrode, depositing electrode material in the capacitor hole, forming the lower electrode includes depositing the electrode material in the capacitor hole after forming the second electrode, and removing excess electrode material by the dry etching process, wet etching process or chemical mechanical polishing process to form the lower electrode flush with the mask layer. In some embodiments, etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer includes removing the mask layer by a dry or wet etching process, and etching the first sacrificial layer by a dry or wet etching process to form the second sacrificial layer having the first preset thickness. In some embodiments, forming an intermediate support layer on the second sacrificial layer includes overlaying an intermediate support material layer on the second sacrificial layer and the lower electrode, forming