CN-115622542-B - Comparator and decision feedback equalization circuit

Abstract

The application provides a comparator and a decision feedback equalization circuit, wherein the comparator comprises a first stage circuit, a second stage circuit, a first switch circuit and a second switch circuit; the first stage circuit comprises a first input circuit and a second input circuit. The first switching circuit and the second switching circuit are respectively used for controlling the conduction of the first input circuit and the second input circuit according to the first feedback signal, the second feedback signal and the clock signal, the first input circuit is used for generating a first differential signal according to the input signal and the first reference signal in a sampling stage when the first switching circuit is conducted, the second input circuit is used for generating a second differential signal according to the input signal and the second reference signal in a sampling stage when the second switching circuit is conducted, and the second stage circuit is used for amplifying and latching the first differential signal or the second differential signal in a regeneration stage so as to output a comparison signal. The application can eliminate the influence of inter-code crosstalk and reduce the working voltage of the comparator.

Inventors

• Gu yinchuan

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260508

Application Date

20210712

Claims (18)

1. 1. A decision feedback equalization circuit is characterized by comprising an N-level comparator, wherein N is a positive integer greater than 1; each stage of comparator is provided with five input ends and one output end, and comprises: the first switching circuit comprises a first stage circuit, a second stage circuit, a first switching circuit and a second switching circuit; the first stage circuit comprises a first input circuit and a second input circuit; The first input circuit is connected with the first switch circuit, the second input circuit is connected with the second switch circuit, the first input circuit and the second input circuit are also connected with the second stage circuit, The first switch circuit and the second switch circuit are respectively provided with three input ends and one output end, wherein one input end is used as a fifth input end of the comparator and used for receiving a clock signal, and the other two input ends are used as a fourth input end of the comparator and used for receiving a first feedback signal and a second feedback signal and used for controlling the conduction of the first input circuit or the second input circuit according to the first feedback signal, the second feedback signal and the clock signal; The first input end of each stage of comparator receives an input signal, the second input end of each stage of comparator receives a first reference signal, and the third input end of each stage of comparator receives a second reference signal; The fourth input end of the 1 st stage comparator is directly connected with the output end of the N stage comparator and is used for receiving the N stage comparison signal output by the N stage comparator as a first feedback signal and a second feedback signal thereof, and the fifth input end of the 1 st stage comparator receives the 1 st clock signal; The fourth input end of the ith comparator is directly connected with the output end of the ith-1 comparator and used for receiving the ith-1 comparison signal output by the ith-1 comparator as a first feedback signal and a second feedback signal thereof, the fifth input end of the ith comparator receives an ith clock signal, wherein i is more than 1 and less than or equal to N, And under the triggering of each stage of clock signal, the comparator compares the input signal with the first reference signal or compares the input signal with the second reference signal according to the comparison signal corresponding to the fourth input end of the comparator so as to output each stage of comparison signal.
2. 2. The decision feedback equalizer circuit of claim 1, wherein, The first input circuit is provided with three input ends and two output ends, wherein one input end is electrically connected with the output end of the first switch circuit, the other two input ends are used for receiving an input signal and a first reference signal, and the first input circuit is also used for generating a first differential signal according to the input signal and the first reference signal in a sampling stage when the first input circuit is conducted; the second input circuit is provided with three input ends and two output ends, one input end is electrically connected with the output end of the second switch circuit, the other two input ends are used for receiving the input signals and second reference signals, and the second input circuit is also used for generating second differential signals according to the input signals and the second reference signals in a sampling stage when the second input circuit is conducted; the second stage circuit is provided with two input ends and two output ends, wherein the input ends of the second stage circuit are respectively and electrically connected with the output ends of the first input circuit and the second input circuit, the output ends of the second stage circuit are the output ends of the comparator, and the second stage circuit is also used for amplifying and latching the first differential signal or the second differential signal in a regeneration stage so as to output a comparison signal.
3. 3. The decision feedback equalization circuit as recited in claim 2, wherein the first stage circuit further comprises a first reset circuit; the first reset circuit is connected with the first input circuit and the second input circuit, and is also connected with a power supply end or a grounding end, The first reset circuit is used for resetting the first input circuit and the second input circuit in a reset stage.
4. 4. The decision feedback equalization circuit of claim 2, wherein the first switching circuit comprises a first on circuit and a first off circuit; the first opening circuit and the first closing circuit are both connected with the control end of the first input circuit, the first closing circuit is also connected with the grounding end or the power end, The first starting circuit is used for conducting the clock signal to the control end of the first input circuit under the control of the first feedback signal; the first closing circuit is used for conducting the control end of the first input circuit to the grounding end or the power end under the control of the second feedback signal so that the first input circuit is closed, and the first feedback signal and the second feedback signal are mutually opposite signals.
5. 5. The decision feedback equalizer circuit of claim 4, wherein the second switching circuit comprises a second on circuit and a second off circuit; The second opening circuit and the second closing circuit are both connected with the control end of the second input circuit, the second closing circuit is also connected with the grounding end or the power end, The second starting circuit is used for conducting the clock signal to the control end of the second input circuit under the control of the second feedback signal; the second closing circuit is configured to conduct, under control of the first feedback signal, the control terminal of the second input circuit to the ground terminal or the power terminal, so that the second input circuit is turned off.
6. 6. The decision feedback equalizer circuit of claim 5, wherein the first turn-on circuit comprises a first switching transistor and the first turn-off circuit comprises a second switching transistor; the second end of the first switch transistor and the first end of the second switch transistor are both connected with the control end of the first input circuit, the second end of the second switch transistor is also connected with the grounding end or the power supply end, the first switch transistor and the second switch transistor are NMOS or PMOS, The control end of the first switch transistor receives the first feedback signal, the first end of the first switch transistor receives the clock signal, and the control end of the second switch transistor receives the second feedback signal.
7. 7. The decision feedback equalizer circuit of claim 6, wherein the second turn-on circuit comprises a third switching transistor, and wherein the second turn-off circuit comprises a fourth switching transistor; The second end of the third switching transistor and the first end of the fourth switching transistor are both connected with the control end of the second input circuit, the second end of the fourth switching transistor is also connected with the grounding end or the power supply end, the third switching transistor and the fourth switching transistor are NMOS or PMOS, The control end of the third switching transistor receives the second feedback signal, the first end of the third switching transistor receives the clock signal, and the control end of the fourth switching transistor receives the first feedback signal.
8. 8. The decision feedback equalizer circuit of claim 7, wherein, When the first feedback signal triggers the first switching transistor and the fourth switching transistor to be in an on state, the second feedback signal triggers the second switching transistor and the third switching transistor to be in an off state, so that the clock signal is input to the control end of the first input circuit through the first switching transistor, and the control end of the second input circuit is connected to the ground end or the power supply end through the fourth switching transistor; When the first feedback signal triggers the first switch transistor and the fourth switch transistor to be in an off state, the second feedback signal triggers the second switch transistor and the third switch transistor to be in an on state, so that a control end of the first input circuit is connected to the grounding end or the power end through the second switch transistor, and the clock signal is input to the control end of the second input circuit through the third switch transistor.
9. 9. The decision feedback equalization circuit of claim 2, wherein the first input circuit comprises a first input transistor, a second input transistor, and a third input transistor; The first end of the first input transistor and the first end of the second input transistor are respectively connected with the second-stage circuit; the second end of the third input transistor is connected with a grounding end or a power supply end; The second end of the first input transistor and the second end of the second input transistor are connected with the first end of the third input transistor; the first input transistor to the third input transistor are NMOS or PMOS, wherein, The control end of the first input transistor receives the input signal; the control end of the second input transistor receives the first reference signal; When the third input transistor is triggered to be in a conducting state by the clock signal, the first input transistor and the second input transistor generate the first differential signal according to the input signal and the first reference signal, and input the first differential signal to the second-stage circuit.
10. 10. The decision feedback equalizer circuit of claim 2, wherein the second input circuit comprises a fourth input transistor, a fifth input transistor, and a sixth input transistor; the first end of the fourth input transistor and the first end of the fifth input transistor are respectively connected with the second-stage circuit; The control end of the sixth input transistor is used as the control end of the second input circuit, and the second end of the sixth input transistor is connected with the grounding end or the power supply end; The second end of the fourth input transistor and the second end of the fifth input transistor are connected with the first end of the sixth input transistor; the fourth to sixth input transistors are NMOS or PMOS, wherein, The control end of the fourth input transistor receives the input signal; the control end of the fifth input transistor receives the second reference signal; When the sixth input transistor is triggered to be in a conducting state by the clock signal, the fourth input transistor and the fifth input transistor generate the second differential signal according to the input signal and the second reference signal, and input the second differential signal to the second stage circuit.
11. 11. The decision feedback equalization circuit of claim 3, wherein the first reset circuit comprises a first reset transistor and a second reset transistor; The first end of the first reset transistor and the first end of the second reset transistor are both connected with the power supply end or the grounding end, the second end of the first reset transistor is connected with the first input circuit, the second end of the second reset transistor is connected with the second input circuit, the first reset transistor and the second reset transistor are PMOS or NMOS, The control ends of the first reset transistor and the second reset transistor both receive the clock signal; When the clock signal triggers the first reset transistor and the second reset transistor to be in a conducting state, the first input circuit is connected to the power supply terminal or the ground terminal through the first reset transistor for resetting, and the second input circuit is connected to the power supply terminal or the ground terminal through the second reset transistor for resetting.
12. 12. The decision feedback equalizer circuit of claim 2, wherein the second stage circuit comprises an output circuit and a second reset circuit; The second reset circuit is connected with the output circuit, the output circuit is also connected with a power supply end or a grounding end, the second reset circuit is also connected with the power supply end or the grounding end, The output circuit is used for amplifying and latching the first differential signal or the second differential signal in a regeneration stage so as to output a comparison signal; The second reset circuit is used for resetting the output circuit in a reset stage.
13. 13. The decision feedback equalization circuit of claim 12, wherein the second reset circuit comprises a third reset transistor and a fourth reset transistor; The first end of the third reset transistor and the first end of the fourth reset transistor are both connected with the power supply end or the grounding end, the second end of the third reset transistor and the second end of the fourth reset transistor are respectively connected with the output circuit, the third reset transistor and the fourth reset transistor are PMOS or NMOS, The control ends of the third reset transistor and the fourth reset transistor both receive the clock signal; When the clock signal triggers the third reset transistor and the fourth reset transistor to be in a conducting state, the output circuit is connected to the power supply terminal or the ground terminal through the third reset transistor and the fourth reset transistor for resetting.
14. 14. The decision feedback equalizer circuit of claim 12, wherein, The output circuit includes a first output transistor, a second output transistor, a third output transistor, a fourth output transistor, a fifth output transistor, and a sixth output transistor; the control terminal of the first output transistor, the first terminal of the second output transistor, the control terminal of the third output transistor, the second terminal of the fourth output transistor and the second terminal of the sixth output transistor are all connected to the first output terminal of the output circuit; The first end of the first output transistor, the control end of the second output transistor, the second end of the third output transistor, the control end of the fourth output transistor and the second end of the fifth output transistor are all connected to the second output end of the output circuit; the second end of the first output transistor and the second end of the second output transistor are respectively connected with the first input circuit, the second input circuit and the second reset circuit; The first end of the third output transistor, the first end of the fourth output transistor, the first end of the fifth output transistor and the first end of the sixth output transistor are all connected with the power supply end or the grounding end; The first output transistor and the second output transistor are NMOS or PMOS, the third output transistor to the sixth output transistor are PMOS or NMOS, wherein, The control terminal of the fifth output transistor and the control terminal of the sixth output transistor both receive the clock signal.
15. 15. The decision feedback equalizer circuit of claim 1, wherein, The voltage of the first reference signal is greater than or less than the voltage of the second reference signal.
16. 16. The decision feedback equalizer circuit of claim 1, wherein, The phase of the i-th clock signal is 360 DEG/N later than the phase of the i-1-th clock signal.
17. 17. Decision feedback equalizer circuit according to any one of claims 1 to 16, characterized in that, When n=4, the fourth input end of the 1 st stage comparator is connected with the output end of the 4 th stage comparator, and receives the 4 th stage comparison signal output by the 4 th stage comparator, and the fifth input end of the 1 st stage comparator receives the 1 st clock signal.
18. 18. The decision feedback equalization circuit as recited in any one of claims 1 to 16, wherein the decision feedback equalization circuit further comprises N latches; the input end of each latch is correspondingly connected with the output end of each stage of comparator to receive each stage of comparison signal, wherein each latch is used for storing each stage of comparison signal to output each stage of latch signal.

Description

Comparator and decision feedback equalization circuit Technical Field The present application relates to integrated circuit design, and more particularly, to a comparator and decision feedback equalizer circuit (Decision Feedback equalization, DFE). Background With the continuous development of computer technology, more and more products are controlled by a computer, so that the intellectualization is realized. However, with the expanding application scenarios, ever increasing demands are also being placed on the performance of computers, including faster operating speeds and lower power consumption. The memory device is an indispensable part of the computer hardware system, and can store instructions and data during the operation of the computer so as to ensure the normal operation of the computer. The comparator is an important component in a common storage device, and the performance of the comparator is improved, so that the overall performance of the computer is improved. Disclosure of Invention The embodiment of the application expects to provide a comparator and a decision feedback equalization circuit, which can eliminate the influence of inter-code crosstalk and reduce the working voltage of the comparator. The technical scheme of the embodiment of the application is realized as follows: the embodiment of the application provides a comparator, which comprises a first stage circuit, a second stage circuit, a first switch circuit and a second switch circuit, wherein the first stage circuit comprises a first input circuit and a second input circuit; the first input circuit is connected with the first switch circuit, and the second input circuit is connected with the second switch circuit; The first switch circuit and the second switch circuit are also respectively connected with a grounding end or a power supply end, and the first input circuit and the second input circuit are also respectively connected with the grounding end or the power supply end; The second-stage circuit is connected with the power end or the grounding end, wherein, The first switch circuit is used for controlling the conduction of the first input circuit according to a first feedback signal, a second feedback signal and a clock signal; the second switch circuit is used for controlling the conduction of the second input circuit according to the first feedback signal, the second feedback signal and the clock signal; The first input circuit is used for generating a first differential signal according to an input signal and a first reference signal in a sampling stage when the first input circuit is conducted; The second input circuit is used for generating a second differential signal according to the input signal and a second reference signal in a sampling stage when the second input circuit is conducted; The second stage circuit is used for amplifying and latching the first differential signal or the second differential signal in a regeneration stage so as to output a comparison signal. In the scheme, the first stage circuit further comprises a first reset circuit; The first reset circuit is connected with the first input circuit and the second input circuit, and is also connected with the power supply end or the grounding end, The first reset circuit is used for resetting the first input circuit and the second input circuit in a reset stage. In the scheme, the first switch circuit comprises a first opening circuit and a first closing circuit; The first opening circuit and the first closing circuit are both connected with the control end of the first input circuit, the first closing circuit is also connected with the grounding end or the power end, The first starting circuit is used for conducting the clock signal to the control end of the first input circuit under the control of the first feedback signal; the first closing circuit is used for conducting the control end of the first input circuit to the grounding end or the power end under the control of the second feedback signal so that the first input circuit is closed, and the first feedback signal and the second feedback signal are mutually opposite signals. In the scheme, the second switch circuit comprises a second opening circuit and a second closing circuit; The second opening circuit and the second closing circuit are both connected with the control end of the second input circuit, the second closing circuit is also connected with the grounding end or the power end, The second starting circuit is used for conducting the clock signal to the control end of the second input circuit under the control of the second feedback signal; the second closing circuit is configured to conduct, under control of the first feedback signal, the control terminal of the second input circuit to the ground terminal or the power terminal, so that the second input circuit is turned off. In the scheme, the first opening circuit comprises a first switch transistor, and the first closing circuit c