CN-115632644-B - Analog switch circuit with latch function

CN115632644BCN 115632644 BCN115632644 BCN 115632644BCN-115632644-B

Abstract

The invention discloses an analog switch circuit with a latch function, which comprises an input shaping circuit, a latch logic control circuit, a level conversion circuit, an output shaping circuit and a switch circuit, wherein the input shaping circuit shapes a received voltage signal and sends the shaped voltage signal to the latch logic control circuit, the latch logic control circuit carries out different logic control on the received voltage signal to generate different first control signals, the level conversion circuit converts the voltage range of the first control signals into a preset voltage range to generate a second control signal, the input end of the output shaping circuit is connected with the output end of the level conversion circuit, and the output end of the output shaping circuit is connected with the switch circuit to generate a switch control signal to control the switch circuit. The invention extends the function of the switch circuit, so that the switch circuit has a latch function, and the reliability of the analog switch circuit is improved.

Inventors

LV JIANGPING
XU SHUXI

Assignees

中国兵器工业集团第二一四研究所苏州研发中心

Dates

Publication Date: 20260505
Application Date: 20221020

Claims (4)

1. An analog switch circuit with a latch function is characterized by comprising an input shaping circuit, a latch logic control circuit, a level conversion circuit, an output shaping circuit and a switch circuit; The input shaping circuit is used for shaping the received voltage signal and sending the shaped voltage signal to the latch logic control circuit; The latch logic control circuit performs different logic control on the received voltage signals and generates different first control signals; The level conversion circuit converts the voltage range of the first control signal into a preset voltage range and generates a second control signal; The input end of the output shaping circuit is connected with the output end of the level conversion circuit, and the output end of the output shaping circuit is connected with the switching circuit to generate a switching control signal to control the switching circuit; The input shaping circuit comprises a first input port, a second input port, a third input port and a fourth input port which are respectively used for accessing a control signal IN, an enable signal EN, a reset signal RS and a read-write signal WR, and comprises a first output port, a second output port, a third output port and a fourth output port which are respectively used for outputting the control signal IN, the enable signal EN, the reset signal RS and the read-write signal WR; the latch logic control circuit comprises a first trigger, a second trigger, a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate and a second NAND gate; the D interface of the first trigger is connected with the first output end of the input shaping circuit and is used for accessing a control signal IN, and the CLK interface of the first trigger is connected with the third output end of the input shaping circuit and is used for accessing a read-write signal WR; The D interface of the second trigger is connected with the second output end of the input shaping circuit and is used for accessing an enable signal EN, the CLK interface of the second trigger is connected with the fourth output end of the input shaping circuit and is used for accessing a read-write signal WR, and the CLR interface of the second trigger is connected with the third output end of the input shaping circuit and is used for accessing a reset signal RS; The output end Q of the first trigger is connected with the input end of the first inverter, and the output end of the first inverter is connected with one of the input ends of the first NAND gate; The inverting output end Q_of the first trigger is connected with the input end of a second inverter, and the output end of the second inverter is connected with one of the input ends of a second NAND gate; the output end Q of the second trigger is respectively connected with the other input ends of the first NAND gate and the second NAND gate, and outputs an ENC signal to the first NAND gate and the second NAND gate; the output end of the first NAND gate is connected with the input end of the third inverter, and the output end of the third inverter is used for outputting an INC signal; The output end of the second NAND gate is connected with the input end of the fourth inverter, and the output end of the fourth inverter is used for outputting an INB signal which is a complementary signal with the INC signal.
2. An analog switch circuit with latch function according to claim 1, wherein: When the reset signal RS is logic 0, the ENC signal is logic 0, the INC signal and the INB signal are both logic 0, and the INC signal and the INB signal form a first control signal for controlling the switch circuit to be in a zero clearing state; when the reset signal RS is logic 1 and the read-write signal WR is logic 1, the ENC signal, the INC signal, and the INB signal are in a hold state, and the INC signal and the INB signal form a first control signal for controlling the switch circuit to be in a hold latch state; When the reset signal RS is logic 1, the read-write signal WR is logic 0, the enable signal EN is logic 1, the signal ENC is logic 1, and the logic signal of the control signal IN is used as a first control signal to control the state of the switch circuit; when the reset signal RS is logic 1, the read-write signal WR is logic 0, and the enable signal EN is logic 0, the ENC signal is logic 0, the INC signal and the INB signal are both logic 0, and the INC signal and the INB signal form a first control signal for controlling the switch circuit to be in an off state.
3. The analog switch circuit with latch function according to claim 1, wherein the predetermined range is a positive and negative power supply voltage range.
4. The analog switch circuit with latch function according to claim 1, wherein the shaped voltage signal is required to satisfy TTL level requirements.

Description

Analog switch circuit with latch function Technical Field The invention belongs to the technical field of analog switches, and particularly relates to an analog switch circuit with a latch function. Background The CMOS analog switch circuit has low on-resistance and quick transmission time, and is widely applied to systems such as signal transmission and signal acquisition. The CMOS analog switch circuit is mainly composed of a control circuit and a transmission circuit, see fig. 1 in particular. The control circuit consists of a PMOS tube P0 and an NMOS tube N0, generates a control signal and controls the on and off of the transmission circuit, thereby completing the signal transmission. With the development of integration of microsystems, analog switches in the system are required to have a data latch function, and generally, analog switches only can transmit real-time data and have no function of latching signals, so that an analog switch circuit with a latch function is urgently needed to be designed. Disclosure of Invention In view of the above problems, the present invention provides an analog switch circuit with a latch function, which extends the switch circuit function to have the latch function, thereby improving the reliability of the analog switch circuit. In order to achieve the technical purpose and achieve the technical effect, the invention is realized by the following technical scheme: an analog switch circuit with a latch function comprises an input shaping circuit, a latch logic control circuit, a level conversion circuit, an output shaping circuit and a switch circuit; The input shaping circuit is used for shaping the received voltage signal and sending the shaped voltage signal to the latch logic control circuit; The latch logic control circuit performs different logic control on the received voltage signals and generates different first control signals; The level conversion circuit converts the voltage range of the first control signal into a preset voltage range and generates a second control signal; The input end of the output shaping circuit is connected with the output end of the level conversion circuit, and the output end of the output shaping circuit is connected with the switching circuit to generate a switching control signal to control the switching circuit. Optionally, the input shaping circuit includes a first input port, a second input port, a third input port and a fourth input port, which are respectively used for accessing a control signal IN, an enable signal EN, a reset signal RS and a read-write signal WR, and the input shaping circuit includes a first output port, a second output port, a third output port and a fourth output port, which are respectively used for outputting the control signal IN, the enable signal EN, the reset signal RS and the read-write signal WR. Optionally, the latch logic control circuit includes a first flip-flop, a second flip-flop, a first inverter, a second inverter, a third inverter, a fourth inverter, a first nand gate, and a second nand gate; the D interface of the first trigger is connected with the first output end of the input shaping circuit and is used for accessing a control signal IN, and the CLK interface of the first trigger is connected with the third output end of the input shaping circuit and is used for accessing a read-write signal WR; The D interface of the second trigger is connected with the second output end of the input shaping circuit and is used for accessing an enable signal EN, the CLK interface of the second trigger is connected with the fourth output end of the input shaping circuit and is used for accessing a read-write signal WR, and the CLR interface of the second trigger is connected with the third output end of the input shaping circuit and is used for accessing a reset signal RS; The output end Q of the first trigger is connected with the input end of the first inverter, and the output end of the first inverter is connected with one of the input ends of the first NAND gate; The inverting output end Q_of the first trigger is connected with the input end of a second inverter, and the output end of the second inverter is connected with one of the input ends of a second NAND gate; the output end Q of the second trigger is respectively connected with the other input ends of the first NAND gate and the second NAND gate, and outputs an ENC signal to the first NAND gate and the second NAND gate; the output end of the first NAND gate is connected with the input end of the third inverter, and the output end of the third inverter is used for outputting an INC signal; The output end of the second NAND gate is connected with the input end of the fourth inverter, and the output end of the fourth inverter is used for outputting an INB signal which is a complementary signal with the INC signal. Optionally, when the reset signal RS is logic 0, the ENC signal is logic 0, the INC signal and the INB signal are both logic 0, an