CN-115641893-B - Content-addressable memory unit, content-addressable memory device, method of operating the same, and method of data search alignment

CN115641893BCN 115641893 BCN115641893 BCN 115641893BCN-115641893-B

Abstract

The invention provides a Content Addressable Memory (CAM) cell, a CAM memory device, a method of operating the CAM memory device, and a method of data search alignment. The CAM cell includes a first flash memory cell having a first end for receiving a first search voltage, a second flash memory cell having a first end for receiving a second search voltage, a second end of the first flash memory cell electrically connected to a second end of the second flash memory cell, wherein the first flash memory cell is serially connected to the second flash memory cell, and a stored data of the content addressable memory cell is determined by a combination of a plurality of threshold voltages of the first flash memory cell and the second flash memory cell.

Inventors

ZENG BAIHAO
LI FENGMIN

Assignees

旺宏电子股份有限公司

Dates

Publication Date: 20260505
Application Date: 20211119
Priority Date: 20211112

Claims (17)

1. A content addressable memory cell comprising: A first flash memory unit, a first end of which is used for receiving a first search voltage; a second flash memory unit, a first end of the second flash memory unit is used for receiving a second search voltage, and a second end of the first flash memory unit is electrically connected with a second end of the second flash memory unit; Wherein the first flash memory cell is connected in series with the second flash memory cell, The method comprises determining a combination of threshold voltages of the first flash memory unit and the second flash memory unit, comparing the first and second search voltages with each other, determining a minimum threshold voltage value for the first flash memory unit when the first predetermined storage data is the storage data, determining a maximum threshold voltage value for the second flash memory unit when the second predetermined storage data is the storage data, determining the maximum threshold voltage value for the second threshold voltage when the third predetermined storage data is the storage data, and determining the minimum threshold voltage value for the first and second threshold voltages when the fourth predetermined storage data is the storage data.
2. A content addressable memory device, comprising: A plurality of first content addressable memory cell strings including a plurality of first content addressable memory cells, each of the first content addressable memory cells including a plurality of flash memory cells, a stored data of each of the first content addressable memory cells being determined by a combination of a plurality of threshold voltages of the flash memory cells of each of the first content addressable memory cells; a first word line driver for providing a plurality of first search voltages and a plurality of second search voltages to the first content addressable memory cells; a plurality of first match lines coupled to the first content addressable memory cells; a plurality of first sense amplifiers coupled to the first match lines, and A decoder coupled to the first sense amplifiers; Wherein the first sense amplifiers sense a plurality of first match currents on the first match lines to generate a plurality of first sensing results when the first search voltages and the second search voltages are applied to the first CAM cells, an Based on the first sensing results, the decoder generates a first matching address indicating that a first search result is the respective address of the matched first content-addressed memory cells; The first search voltage of the first search voltages and the first search voltage of the second search voltages are determined based on search data, the search data is compared with the storage data, when the storage data is a first set storage data, a first threshold voltage of a first flash memory unit of each flash memory unit is a minimum threshold voltage value, when the storage data is a second set storage data, a second threshold voltage of a second flash memory unit of each flash memory unit is a maximum threshold voltage value, when the storage data is a second set storage data, the first threshold voltage is the maximum threshold voltage value, the second threshold voltage is the minimum threshold voltage value, when the storage data is a third set storage data, the first threshold voltage and the second threshold voltage are both the minimum threshold voltage value, and when the storage data is a fourth set storage data, the first threshold voltage and the second threshold voltage are equal to or larger than the maximum threshold voltage value.
3. The content addressable memory device of claim 2, wherein in the first content addressable memory cell, the first search voltage is a minimum search voltage value and the second search voltage is a maximum search voltage value when the search data is a first predetermined search data, the first search voltage is the maximum search voltage value and the second search voltage is the minimum search voltage value when the search data is a second predetermined search data, and the first search voltage and the second search voltage are both the maximum search voltage value when the search data is a third predetermined search data, wherein the first search result is a match when the first match current occurs on the first match line.
4. The content-addressed memory device of claim 2, wherein the content-addressed memory device further comprises: A plurality of second content addressable memory cell strings including a plurality of second content addressable memory cells, each of the second content addressable memory cells including a plurality of flash memory cells, a stored data of each of the second content addressable memory cells being determined by a combination of a plurality of threshold voltages of the flash memory cells of each of the second content addressable memory cells; A second word line driver for providing a plurality of third search voltages and a plurality of fourth search voltages to the second content addressable memory cells; a plurality of second match lines coupled to the second content addressable memory cells; a plurality of second sense amplifiers coupled to the second match lines, and When the third search voltages and the fourth search voltages are applied to the second content addressing memory cells, the second sense amplifiers sense second matching currents on the second matching lines to generate second sensing results; The decoder generates the first matching address and a second matching address according to a plurality of logic operation results of the first sensing results and the second sensing results, wherein the second matching address indicates that a second search result is the respective address of the matched second content-addressed memory units.
5. The content-addressed memory device of claim 4, further comprising: Logic gates coupled between the first sense amplifiers and the decoder or between the second sense amplifiers and the decoder.
6. A method of operation of a content addressable memory device, comprising: Programming a plurality of content addressable memory cells, each of the content addressable memory cells comprising a plurality of flash memory cells, a stored data of each of the content addressable memory cells being determined by a combination of a plurality of threshold voltages of the flash memory cells of each of the content addressable memory cells, the content addressable memory cells being coupled to a plurality of match lines; Applying a plurality of first search voltages and a plurality of second search voltages to the content-addressed memory cells; Sensing a plurality of matching currents on the matching lines to generate a plurality of sensing results, and Generating a matching address indicating a search result as the respective address of the matched content-addressed memory cells according to the sensing results; The first search voltage of the first search voltages and the first search voltage of the second search voltages are determined based on search data, the search data is compared with the storage data, when the storage data is a first set storage data, a first threshold voltage of a first flash memory unit of each flash memory unit is a minimum threshold voltage value, when the storage data is a second set storage data, a second threshold voltage of a second flash memory unit of each flash memory unit is a maximum threshold voltage value, when the storage data is a second set storage data, the first threshold voltage is the maximum threshold voltage value, the second threshold voltage is the minimum threshold voltage value, when the storage data is a third set storage data, the first threshold voltage and the second threshold voltage are both the minimum threshold voltage value, and when the storage data is a fourth set storage data, the first threshold voltage and the second threshold voltage are equal to or larger than the maximum threshold voltage value.
7. The method of claim 6, wherein in the CAM cell, the first search voltage is a minimum search voltage and the second search voltage is a maximum search voltage when the search data is a first predetermined search data, the first search voltage is the maximum search voltage and the second search voltage is the minimum search voltage when the search data is a second predetermined search data, and the first search voltage and the second search voltage are both the maximum search voltage when the search data is a third predetermined search data, wherein the search result is a match when the match current is present on the match line.
8. A content addressable memory device, comprising: A plurality of strings of content addressable memory cells, each of the strings of content addressable memory cells comprising a plurality of content addressable memory cells, each of the content addressable memory cells comprising a plurality of flash memory cells in series, individual stored data of each of the strings of content addressable memory cells being related to a portion of a reference string (REFERENCE STRING) of data; a word line decoder and driver for providing search voltages to the content addressable memory cells, the word line decoder and driver determining the search voltages applied to the content addressable memory cells according to a data segment (read) during a plurality of alignment rounds; A plurality of match lines coupled to the content addressable memory cells; a plurality of sensing and counting circuits coupled to the match lines, and A decoder coupled to the sensing counter circuits; In the comparison rounds, when the search voltages are applied to the content addressable memory cells, the sensing and counting circuits sense and count matching currents on the matching lines to generate a plurality of counting results, and the decoder determines whether the data segment matches the reference serial data according to the counting results of the sensing and counting circuits.
9. The content addressable memory device of claim 8, wherein the decoder determines that the data segment matches the reference serial data when a highest of the count results is above a threshold.
10. The device of claim 8, wherein in each of the alignment rounds, the word line decode and driver selects a seed data from the data segment, the word line decode and driver determining the search voltages applied to the content addressable memory cells based on the seed data.
11. The device of claim 10, wherein the word line decode and driver applies a predetermined search data to the series of content-addressed memory cells or stores a predetermined store data to at least one content-addressed memory cell of the series of content-addressed memory cells when an effective length of the seed data is less than a number of content-addressed memory cells of the series of content-addressed memory cells in the alignment rounds.
12. The device of claim 8, wherein determining whether to store an invalid datum in the series of content addressable memory cells is based on the reference series data.
13. A method of data search alignment, the method comprising: Programming a plurality of content addressable memory cells, each of the content addressable memory cells comprising a plurality of serial flash memory cells, individual stored data of each of the strings of content addressable memory cells being related to a portion of a reference string (REFERENCE STRING) of data, the content addressable memory cells being coupled to a plurality of match lines; applying search voltages to the content addressable memory cells, wherein in a plurality of alignment rounds, a data segment (read) is used to determine the search voltages applied to the content addressable memory cells; sensing and counting a plurality of matching currents on the matching lines in the comparison rounds to generate a plurality of counting results, and And determining whether the data segment matches the reference serial data according to the counting results.
14. The method of claim 13 wherein the data segment is determined to match the reference serial data when a highest of the count results is above a threshold.
15. The method of claim 13 wherein, in each of the alignment rounds, a seed data is selected from the data segment, the seed data being used to determine the search voltages applied to the content addressed memory cells.
16. The method of claim 15 wherein in the comparison rounds, when an effective length of the seed data is less than a number of content addressable memory cells, applying a predetermined search data to the content addressable memory cells or storing a predetermined store data to at least one content addressable memory cell of the string of content addressable memory cells.
17. The method of claim 13 wherein the reference serial data is used to determine whether to store an invalid data in the content addressable memory cells.

Description

Content-addressable memory unit, content-addressable memory device, method of operating the same, and method of data search alignment Technical Field The present invention relates to a content addressable memory (Content Addressable Memory, CAM) unit, a CAM memory device, an operating method thereof, and a data search comparison method, and more particularly, to a CAM unit, a CAM memory device, an operating method thereof, and a data search comparison method that can be used for implementing an In-memory search (IMS) system. Background With the advent of big data and Artificial Intelligence (AI) hardware accelerators, data search and data alignment are important functions. Existing ternary content addressable memory (Ternary Content Addressable Memory, TCAM) can be used to implement the highly parallel search (HIGHLY PARALLEL SEARCHING). Conventional TCAMs are typically composed of static random access memories (Static Random Access Memory, SRAM), and therefore have low storage densities and high access powers. In order to save power consumption by dense storage density, TCAM-based nonvolatile memory arrays have recently been proposed. Compared to SRAM-based TCAMs with 16 transistors (16T), resistive random access memory (RESISTIVE RANDOM ACCESS MEMORY, RRAM) with 2 transistors and 2 resistive (2T 2R) structures have recently been developed to reduce cell area. Standby power consumption (standby power consumption) may also be improved by using a RRAM-based non-volatile TCAM. However, the RRAM has a limited resistivity (R-ratio) and is difficult to distinguish between a matching state and a non-matching state, so that the RRAM is insufficient to perform a parallel search for a large amount of data. Compared to the 2T2R structure, TCAM arrays based on ferroelectric field effect transistors (Ferroelectric FETs, fefets) can provide higher on/off current ratios (on/off ratios) and dense memory arrays, but the on/off current ratios of FeFET devices are still not high enough to affect matching accuracy, and thus are not suitable for long word search designs. In addition, in genomic analysis of DNA, the number of DNA or RNA sequences is measured using the next generation sequencing (Next Generation Sequencing, NGS) technique. The genome is cut and sequenced into sets of data fragments (reads), which are then mapped to a reference genome, referred to as a read map (READ MAPPING), for genome matching and mapping. The read map is the most time consuming part of the genome analysis process, as it requires a huge amount of memory and the communication between the memory and the computing unit (CPU/GPU) limits the read map. Therefore, what is needed is a content addressable memory (Content Addressable Memory, CAM) unit, a content addressable memory device, methods of operating the same, and methods of data search alignment that provide high matching accuracy and are suitable for long word search designs when used to implement an In-memory search (IMS) system and genomic analysis. BRIEF SUMMARY OF THE PRESENT DISCLOSURE According to one embodiment of the present invention, a content addressable memory cell is provided, comprising a first flash memory cell having a first terminal for receiving a first search voltage, a second flash memory cell having a first terminal for receiving a second search voltage, a second terminal of the first flash memory cell being electrically connected to a second terminal of the second flash memory cell, wherein the first flash memory cell is serially connected to the second flash memory cell, and a stored data of the content addressable memory cell is determined by a combination of a plurality of threshold voltages of the first flash memory cell and the second flash memory cell. According to another embodiment of the present invention, a content addressable memory device is provided, comprising a plurality of first content addressable memory cell strings, the first content addressable memory cell strings comprising a plurality of first content addressable memory cells, each of the first content addressable memory cells comprising a plurality of flash memory cells, a storage data of each of the first content addressable memory cells being determined by a combination of a plurality of threshold voltages of the flash memory cells of each of the first content addressable memory cells, a first word line driver for providing a plurality of first search voltages and a plurality of second search voltages to the first content addressable memory cells, a plurality of first match lines coupled to the first content addressable memory cells, a plurality of first sense amplifiers coupled to the first match lines, and a decoder coupled to the first sense amplifiers, wherein the first sense amplifiers sense a plurality of first sense currents on the first match lines to generate a plurality of first sense currents when the first search voltages and the second search voltages are applied to the first content