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CN-115643792-B - Preparation method of PIP capacitor

CN115643792BCN 115643792 BCN115643792 BCN 115643792BCN-115643792-B

Abstract

The invention relates to the field of CMOS integrated circuit manufacturing process, and discloses a preparation method of a PIP capacitor, which comprises the steps of firstly reducing the film stress of a WSi x of a lower polar plate of the PIP capacitor by injection, and then reducing the parasitic SiO 2 on the surface of the lower polar plate of the PIP capacitor by dry etching. The reliability of PIP capacitance can be improved by reducing the stress of the bottom plate WSi x film through implantation, the implantation energy is selected in such a way that the depth (R p +3ΔR p ) of the implanted Gaussian distribution reaches 80% of the thickness of the whole WSi x film, the stress of the implanted WSi x film is reduced by one order of magnitude, and the phosphorus element is selected to eliminate the stress of the WSi x film because the N-type polycrystal implantation is doped with the phosphorus element frequently. Meanwhile, the phosphorus injection can also increase the doping concentration of the polycrystal, and the depletion of the polycrystal is reduced.

Inventors

  • CHEN XIAOYU
  • XUE DONGFENG
  • ZHAO JIE
  • LIU CUNSHENG
  • CHEN BAOZHONG

Assignees

  • 西安微电子技术研究所

Dates

Publication Date
20260505
Application Date
20221031

Claims (7)

  1. 1. The preparation method of the PIP capacitor is characterized by comprising the following steps of: Step 1, depositing an undoped polysilicon layer on a silicon substrate wafer which is subjected to well injection, active region photoetching and etching, field isolation and gate oxide, and carrying out N-type diffusion doping on the polysilicon layer; Step 2, depositing a WSi x layer on the polysilicon layer subjected to N-type diffusion doping; step 3, photoetching and etching the polysilicon layer after depositing the WSi x layer, removing photoresist after etching, and forming a PIP capacitor lower polar plate; Step 4, performing PIP capacitance reverse lithography on the PIP capacitance lower electrode plate, and injecting phosphorus element into the WSi x layer of the PIP capacitance lower electrode plate to enable the WSi x layer to be amorphized, so that stress of the WSi x film is reduced; The energy range of phosphorus element injection is 20-100 keV, the injection dosage is 1 multiplied by 10 15 ~1×10 16 /cm 2 , wherein the injection energy is selected in such a way that the depth (R p +3ΔR p ) of the injection Gaussian distribution reaches 80% of the thickness of the whole WSi x film, the phosphorus element injection also increases the doping concentration of the first polycrystal under the WSi x layer, and the polycrystal depletion is reduced; Step 5, etching the surface of the WSi x layer of the PIP capacitor lower electrode plate after phosphorus element injection, removing SiO 2 parasitic on the surface of the WSi x layer by dry etching, and removing photoresist after etching; Etching the surface of a WSi x layer of the lower polar plate of the PIP capacitor after phosphorus element injection, removing SiO 2 parasitic on the surface of the WSi x layer by dry etching, wherein CF 4 and CHF 3 are adopted as main etching gases, the etching selection ratio of SiO 2 /WSi x is 10:1, and removing the photoresist masking layer of the reverse-edition photoetching of the PIP capacitor after etching; step 6, depositing a PIP capacitor dielectric layer on the photoresist-removed PIP capacitor lower polar plate; Step 7, depositing PIP capacitor upper polar plate polycrystal on the PIP capacitor dielectric layer and carrying out N-type injection doping; step 8, photoetching and etching are carried out on the polycrystalline of the upper polar plate of the PIP capacitor, photoresist is removed after etching, and the PIP capacitor is formed; photoetching and etching the upper polar plate polycrystal of the PIP capacitor, wherein photoetching comprises gluing, exposing and developing, forming a PIP capacitor etching masking layer on the upper polar plate polycrystal of the PIP capacitor by using photoetching glue, and removing glue by a dry method and a wet method after etching to form the PIP capacitor.
  2. 2. The method for manufacturing the PIP capacitor according to claim 1, wherein in the step 1, N-well implantation, P-well implantation, active region lithography and etching, field isolation and gate oxide growth are performed on a wafer of a silicon substrate, an undoped polysilicon layer with a thickness of 1500-2500 a is deposited by a CVD method, and N-type diffusion doping is performed on the polysilicon layer by a liquid phosphorus source POCl 3 .
  3. 3. The method of claim 1, wherein in step 2, a WSi x layer of 500-2000 a is deposited on the N-doped polysilicon layer by CVD or PVD.
  4. 4. The method of claim 1, wherein in step 3, the polysilicon layer after depositing the WSi x layer is subjected to photolithography and etching, wherein the photolithography includes photoresist coating, exposure and development, and the etching mask layer is formed on the polysilicon layer after photolithography by using photoresist.
  5. 5. The method for manufacturing a PIP capacitor according to claim 1, wherein in step 4, PIP capacitor inverse lithography is performed on a lower plate of the PIP capacitor, wherein the lithography includes photoresist coating, exposure and development, and a capacitor inverse mask layer is formed on the lower plate of the PIP capacitor by using the photoresist, wherein the size of the capacitor inverse mask layer is 0-0.2 μm larger than the PIP capacitor, and the polarities of the layout layers of the capacitor inverse lithography and the PIP capacitor lithography are opposite.
  6. 6. The method for manufacturing the PIP capacitor according to claim 1, wherein in the step 6, a SiO 2 or Si 3 N 4 dielectric layer is deposited by using a CVD method to serve as the PIP capacitor dielectric layer, the thickness of the SiO 2 dielectric layer is 100-500A, and the thickness of the Si 3 N 4 dielectric layer is 50-300A.
  7. 7. The method for manufacturing a PIP capacitor according to claim 1, wherein in step 7, an undoped polysilicon layer with a thickness of 1500-2500A is deposited by a CVD method, and N-type doping is achieved by implanting phosphorus element with an energy range of 50-80 keV and an implantation dose of 1-2×10 16 /cm 2 .

Description

Preparation method of PIP capacitor Technical Field The invention relates to the field of CMOS integrated circuit manufacturing processes, in particular to a preparation method of a PIP capacitor. Background In large scale integrated circuit fabrication processes, doped polysilicon is often used as the gate electrode and poly interconnect material. With the continuous improvement of the circuit integration level, the size of the device is further reduced, the polycrystalline thickness is continuously reduced, the polycrystalline resistance is increased instead, and the requirements of lower resistance of the gate electrode and the polycrystalline interconnection of the device cannot be met. In sub-micron integrated circuit fabrication processes, doped polysilicon is replaced with tungsten silicide (WSi x, 1.5< x < 2.5) polysilicon-metal silicide (polycide) which has a resistance value that is more than an order of magnitude lower. In the WSi x polycide process, polysilicon is grown first, then a layer of silicide WSi x with low resistance is deposited through diffusion doping of polysilicon to form a polycide laminated structure, so that the resistance of the gate electrode is reduced. Meanwhile, the laminated structure can be used as a lower electrode plate of a polysilicon-insulating layer-polysilicon (English name is Poysilicon-Insulator-Poysilicon, abbreviated as PIP) capacitor, so that a digital-analog mixing process is realized. However, WSi x has two disadvantages as a PIP capacitor bottom plate. The first disadvantage is that WSi x is very stressed, reaching 5-15X 10 8 Pa. In the polycide CMOS process, WSi x is deposited and then subjected to a number of high temperature processes, such as sidewall deposition, source drain annealing (or junction pushing), and dielectric reflow. In the high-temperature process, the self stress exceeds the adhesion force to the underlying polysilicon, so that the WSi x layer is very easy to curl upwards and peel off and separate (peeling) in a large area, and the stability and the reliability of the PIP capacitor are seriously affected. The second disadvantage is that the surface of WSi x is easily oxidized, which is particularly obvious in the high temperature process, and the lower plate of PIP capacitor forms parasitic SiO 2 layer capacitor, resulting in reduced capacitance value and poor precision of PIP capacitor. For WSi x stress, the process can be optimized to use a thin film growth method with less stress. "Chemical Vapor Deposition of Tungsten and Tungsten Silicides for VLSI/ULSI Applications" (press: WILLIAM ANDREW, 12/31/204 199) proposed that the exfoliation of WSi x film after SiH 2CL2 was substituted for SiH 4 as a reaction gas was significantly reduced by ."Analysis of stress in chemical vapor deposition tungsten silicide film"(Journal of Applied Physics,1985 at 58/4194) and that the increase in the Si/W composition ratio could significantly reduce the stress. However, even under optimal growth conditions, the stress of WSi x fluctuates greatly, and WSi x Peeling is difficult to avoid. the process method adopted at present is to deposit a CAP layer (CAP) of SiO 2 after the deposition of the WSi x film, see U.S. Pat. No. 5, polycide gate MOSFET process for integrated circuits (U.S. Pat. No. 5089432,1992, 2, 18). because the film stress of SiO 2 is-10 9 Pa, the tensile stress of the WSi x film can be effectively relieved. Studies of the WSi Polycide process (electronics and packaging, page 29, 12 of 2012) indicate that the CAP layer can only maintain the stress of the current WSi x film and cannot reduce the stress of the WSi x film. Furthermore, the CAP layer adds complexity to the process, and particularly the topography of the poly etch is difficult to control. For surface Oxidation of WSi x, "Oxidation MECHANISMS IN WSI 2 THIN FILMS" (APPLIED PHYSICS LETTERS,1978, page 33, page 76) indicates that Si in the underlying poly-crystal of WSi x moves to the upper surface of WSi x and reacts with oxygen to form parasitic SiO 2 during high temperature temperatures of 800-1100 ℃. Since the WSi x undergoes a plurality of high temperature processes greater than 800 ℃ after deposition in a polycide CMOS process, the quality and thickness of the parasitic SiO 2 film formed on the WSi x surface is difficult to control accurately. Disclosure of Invention In order to overcome the defects in the prior art, the invention aims to provide a preparation method of a PIP capacitor, which aims to solve the technical problem of low capacitance of the PIP capacitor in the metal silicide process in the prior art. The invention is realized by the following technical scheme: The preparation method of the PIP capacitor comprises the following steps: Step 1, depositing an undoped polysilicon layer on a silicon substrate wafer which is subjected to well injection, active region photoetching and etching, field isolation and gate oxide, and carrying out N-type diffusion dop