CN-115656780-B - High-speed interface testing device, system and method

CN115656780BCN 115656780 BCN115656780 BCN 115656780BCN-115656780-B

Abstract

The invention relates to a high-speed interface testing device, a high-speed interface testing system and a high-speed interface testing method, and relates to the technical field of integrated circuit testing. The device comprises a chip interface to be tested, an externally hung chip interface, a first resistance board, a second resistance board, a first SMA interface, a second SMA interface, a signal integrity test board and a PSSL board card, wherein in three paths of mutually connected 0-ohm resistors, the first path of mutually connected 0-ohm resistors are connected with the PSSL board card, the second path of mutually connected 0-ohm resistors are connected with the externally hung chip interface, the third path of mutually connected 0-ohm resistors are connected with the first SMA interface and the second SMA interface, the first SI board is connected with the first SMA interface and the second SMA interface respectively, and the chip interface to be tested is used for being connected with a high-speed interface chip. Through the arrangement of the three-way loop, different requirements test items can be tested on the high-speed interface chip in the burning process, and a multifunctional and multi-parameter efficient test mode is provided for the high-speed interface.

Inventors

WANG ZHILI
ZHANG KAIHONG
XI LIUHUA
WANG YIWEI
LI XIAOLIANG

Assignees

无锡中微腾芯电子有限公司

Dates

Publication Date: 20260505
Application Date: 20221107

Claims (7)

1. The device is characterized by comprising a chip interface to be tested, an externally hung chip interface, a first resistance board, a second resistance board, a first SMA interface, a second SMA interface, an SI board and a PSSL board card; the first resistance plate and the second resistance plate are respectively provided with three paths of mutually connected 0 ohm resistors; among the three paths of interconnected 0 ohm resistors, a first path of interconnected 0 ohm resistor is connected with the PSSL board, a second path of interconnected 0 ohm resistor is connected with the plug-in chip interface, a third path of interconnected 0 ohm resistor is connected with the first SMA interface and the second SMA interface, and the SI board is respectively connected with the first SMA interface and the second SMA interface; The chip interface to be tested is used for being connected with the high-speed interface chip; the plug-in chip interface is used for being connected with a plug-in chip, and the plug-in chip is used for assisting in testing of the high-speed interface chip; The three paths of the interconnected 0 ohm resistors correspond to three paths of loops altogether, the first path of the interconnected resistors are connected with the PSSL board card to form a first path of loop, the 0 ohm resistor, the plug-in chip and the chip to be tested, which are interconnected with the second path of the test machine, form a second path of loop, and the third path of the interconnected 0 ohm resistor, the first SMA interface, the second SMA interface and the SI board form the loop.
2. A high-speed interface test system, characterized in that the high-speed interface test system comprises a test machine and the high-speed interface test device according to claim 1; The test machine is in communication connection with the high-speed interface test device, and is provided with computer equipment.
3. A method for testing a high-speed interface, wherein the method is applied to a computer device in a high-speed interface testing system according to claim 2, and the method comprises: determining a chip to be tested connected with a high-speed interface testing device and an externally hung chip corresponding to the chip to be tested; Generating a burning decomposition program in response to receiving a chip installation completion signal to be detected and an external chip installation completion signal; configuring a burning decomposition program, and controlling a test machine and the high-speed interface test device to start a test process; reading a burning byte corresponding to the burning decomposition program; And determining a test result corresponding to the chip to be tested based on a byte burning result corresponding to the burning byte, wherein test items in the byte burning result are determined by the chip to be tested, the PSSL board card and the plug-in chip.
4. The method for testing a high-speed interface according to claim 3, wherein determining the test result corresponding to the chip under test based on the byte-recording result corresponding to the recording byte comprises: determining the byte number corresponding to the burnt byte; determining byte content corresponding to the burnt bytes in response to the byte number being consistent with a preset byte number; And responding to the byte content consistent with the preset byte content, and determining that the chip to be tested passes the test.
5. The method for testing a high-speed interface according to claim 4, further comprising: Executing the burn-in program in response to the byte number not being consistent with the preset byte number or the byte content not being consistent with the preset byte content; and responding to the times of executing the burn-in program reaching an execution time threshold value, and determining that the chip to be tested fails the test.
6. A method of testing a high-speed interface according to claim 3, wherein said configuring a burn-in decomposition program comprises: determining a pin address corresponding to the chip to be tested; And generating the burning decomposition program based on the pin address.
7. A method of testing a high speed interface according to claim 3, further comprising: And modifying the rolling code part corresponding to the burning file in the burning decomposition program.

Description

High-speed interface testing device, system and method Technical Field The present invention relates to the field of integrated circuit testing technologies, and in particular, to a high-speed interface testing device, a high-speed interface testing system, and a high-speed interface testing method. Background High-speed interfaces are applied not only to personal computers, servers and communication devices, but also to digital consumer electronics, medical devices, broadcasting devices, semiconductor manufacturing and testing devices, and many other electronic devices and applications. Meanwhile, as technology is developed and evolved, high-speed interfaces are generally integrated with multiple types of functions. To ensure the performance of the high-speed interface, the high-speed interface is usually tested by an integrated circuit automatic tester (Automatic Test Equipment, ATE) test system in the related art. However, for high-speed interfaces compatible with multiple test schemes, conventional ATE tests cannot meet all test item requirements, and based on this, how to provide an ATE test board design method for a high-speed interface is a technical problem to be solved by those skilled in the art. Disclosure of Invention The invention aims to overcome the defects existing in the prior art, thereby providing a high-speed interface testing device, a high-speed interface testing system and a high-speed interface testing method and providing a multifunctional and multi-parameter high-efficiency testing mode for the high-speed interface. The technical scheme is as follows: In one aspect, a high-speed interface testing apparatus is provided, the high-speed interface testing apparatus includes a chip interface to be tested, a plug-in chip interface, a first resistive plate, a second resistive plate, a first SMA (SubMiniature version A) interface, a second SMA interface, a signal integrity test (SIGNAL INTEGRITY, SI) plate, and a PSSL board card (please provide a full scale of PSSL); The first resistance plate and the second resistance plate are respectively provided with three paths of 0 ohm resistors which are connected with each other; among the three paths of interconnected 0 ohm resistors, the first path of interconnected 0 ohm resistor is connected with the PSSL board card, the second path of interconnected 0 ohm resistor is connected with the plug-in chip interface, the third path of interconnected 0 ohm resistor is connected with the first SMA interface and the second SMA interface, and the first SI board is respectively connected with the first SMA interface and the second SMA interface; The chip interface to be tested is used for being connected with the high-speed interface chip; The plug-in chip interface is used for being connected with the plug-in chip, and the plug-in chip is used for assisting in testing of the high-speed interface chip. In another aspect, a high-speed interface test system is provided, the system comprising a test station, a computer device, and a high-speed interface test apparatus as described above, the test station and the high-speed interface test apparatus being communicatively connected, the test station being configured with the computer device. In another aspect, there is provided a method for testing a high-speed interface, the method being applied to a computer device in a high-speed interface test system as described above, the method comprising: Determining a chip to be tested connected with the high-speed interface testing device and an externally hung chip corresponding to the chip to be tested; generating a burning decomposition program in response to receiving a chip installation completion signal to be detected and an external core installation completion signal; configuring a burning decomposition program, and controlling a test machine and a high-speed interface test device to start a test process; reading a burning byte corresponding to the burning decomposition program; Based on the byte burning result corresponding to the burning bytes, determining a test result corresponding to the chip to be tested, wherein test items in the byte burning result are determined by the chip to be tested, the PSSL board card and the plug-in chip. The technical scheme provided by the invention has the beneficial effects that at least: In the device for testing the chip to be tested, through carrying out three groups of 0 omega resistors correspondingly connected on the first resistance board and the second resistance board and forming a connection mode of three circuits, the chip to be tested and the test machine form an external loop in the test process, the chip to be tested and the plug-in chip form a direct connection, and a verification loop is formed through an SMA interface and an SI board, in the process of executing the test through the burning of the high-speed interface, the test parameters can be determined through the direct connection of the PSSL board and