CN-115692453-B - Array substrate, preparation method thereof, light-emitting device and spliced display device

CN115692453BCN 115692453 BCN115692453 BCN 115692453BCN-115692453-B

Abstract

The application provides an array substrate, a preparation method thereof, a light-emitting device and a spliced display device. The array substrate comprises a device region, a peripheral region adjacent to the device region, an interlayer dielectric layer and a plurality of devices, wherein the device region and the peripheral region comprise a substrate and a reflecting layer positioned on the substrate, the interlayer dielectric layer is at least positioned between the substrate and the reflecting layer, the reflecting layer is provided with a plurality of hollowed-out areas along the direction perpendicular to the substrate, the devices are positioned in the hollowed-out areas, the orthographic projection of the part of the reflecting layer positioned on the device region on the substrate overlaps with the orthographic projection of the interlayer dielectric layer on the substrate, the part of the peripheral region covers the part of the substrate positioned on the peripheral region, and the outline of the substrate is consistent with the outline of the peripheral region of the array substrate. The peripheral area of the array substrate can reflect light, so that the problem that the optical brightness difference of different areas of the array substrate is large is solved, and the display effect of the spliced display device prepared by the array substrate is improved.

Inventors

GAO LIANG
TANG HAI

Assignees

合肥京东方星宇科技有限公司
京东方科技集团股份有限公司

Dates

Publication Date: 20260508
Application Date: 20210730

Claims (16)

1. An array substrate, characterized by comprising: A device region; a peripheral region adjacent to the device region; The device region and the peripheral region each comprise a substrate and a reflective layer on the substrate; the device region also comprises an interlayer dielectric layer and a plurality of devices, wherein the interlayer dielectric layer is at least positioned between the substrate and the reflecting layer, the reflecting layer is provided with a plurality of hollowed-out areas along the direction vertical to the substrate, and the devices are positioned in the hollowed-out areas; The device comprises a substrate, a reflection layer, a substrate, a device and an interlayer dielectric layer, wherein the orthographic projection of the part of the reflection layer, which is positioned in the device region, on the substrate overlaps with the orthographic projection of the interlayer dielectric layer on the substrate, the part of the reflection layer, which is positioned in the peripheral region, covers the part of the substrate, which is positioned in the peripheral region, and the outline of the substrate is consistent with the outline of the peripheral region; The array substrate further comprises an auxiliary reflecting part, wherein the auxiliary reflecting part is positioned on the interlayer dielectric layer and is connected with the reflecting layer; the auxiliary reflecting part comprises a first reflecting part and a second reflecting part, and the first reflecting part and the second reflecting part are of an integrated structure; the hollowed-out area exposes a partial area of the interlayer dielectric layer, the orthographic projection of the first reflecting part on the substrate is positioned in the hollowed-out area, and the first reflecting part is in direct contact with the interlayer dielectric layer; the second reflecting part is in direct contact with the surface of the reflecting layer, which is far away from the substrate, and the orthographic projection of the second reflecting part on the substrate is overlapped with the orthographic projection of the reflecting layer on the substrate; The array substrate further comprises a plurality of packaging units corresponding to the devices, orthographic projection of the packaging units on the substrate covers orthographic projection of the devices on the substrate, and orthographic projection of the packaging units on the substrate is overlapped with orthographic projection portions of the reflecting layers on the substrate.
2. The array substrate of claim 1, wherein the reflective layer comprises a first reflective sub-layer and a second reflective sub-layer, the second reflective sub-layer being located on a side of the first reflective sub-layer away from the substrate; The orthographic projection of the part of the first reflecting sub-layer, which is positioned in the device region, on the substrate is overlapped with the orthographic projection part of the interlayer dielectric layer on the substrate, and the part of the substrate, which is positioned in the peripheral region, is also covered by the first reflecting sub-layer; the orthographic projection of the second reflective sub-layer on the substrate is located within the orthographic projection of the first reflective sub-layer on the substrate.
3. The array substrate of claim 2, wherein an orthographic projection of the second reflective sub-layer on the substrate is located in the device region; the orthographic projection of the second reflecting sub-layer on the substrate and the orthographic projection of the part of the first reflecting sub-layer, which is positioned in the peripheral area, on the substrate are not overlapped with each other.
4. The array substrate of claim 2, wherein orthographic projections of the second reflective sub-layer on the substrate are located in the peripheral region and the device region; the orthographic projection of the part of the second reflecting sub-layer positioned in the peripheral area on the substrate is overlapped with the orthographic projection of the part of the first reflecting sub-layer positioned in the peripheral area on the substrate.
5. The array substrate of claim 2, wherein the first and second reflective sublayers are the same thickness in a direction perpendicular to the substrate.
6. The array substrate according to claim 1, wherein the device region of the array substrate further comprises a buffer layer and a first conductive layer sequentially arranged on the substrate, and the interlayer dielectric layer is positioned on one side of the first conductive layer away from the substrate; The interlayer dielectric layer comprises a first insulating layer and a first flat layer, and the first flat layer is at least positioned between the first insulating layer and the reflecting layer.
7. The array substrate of claim 6, wherein the device region of the array substrate further comprises a second conductive layer, a second insulating layer, a second flat layer, and a third insulating layer sequentially stacked on the buffer layer, the third insulating layer being located on a side of the first conductive layer away from the first insulating layer.
8. The array substrate of claim 6, wherein the first conductive layer comprises at least one first pad and at least one second pad, the interlayer dielectric layer has a plurality of first openings and a plurality of second openings along a direction perpendicular to the substrate, the first openings exposing areas where the first pads are located, and the second openings exposing areas where the second pads are located; the first bonding pad is electrically connected with the first welding pin of the device through the first opening, and the second bonding pad is electrically connected with the second welding pin of the device through the second opening.
9. The array substrate of claim 8, further comprising a plurality of support posts, the support posts being located on a side of the reflective layer remote from the substrate, and wherein an orthographic projection of the support posts onto the substrate and an orthographic projection of the device onto the substrate do not overlap each other.
10. A light-emitting device comprising the array substrate according to any one of claims 1 to 9.
11. The light-emitting device according to claim 10, further comprising a diffusion plate, a quantum dot film, a diffusion sheet, and a composite film, which are stacked in this order; the diffusion plate is located on the light emitting side of the array substrate.
12. A tiled display device comprising at least two light emitting devices according to claim 10 or 11.
13. A method for preparing an array substrate, wherein the method is applied to preparing the array substrate according to any one of claims 1 to 9, and comprises the following steps: The method comprises the steps of providing a motherboard substrate, wherein the motherboard substrate is divided into at least one device area and a cutting area adjacent to the device area; Forming an interlayer dielectric layer on the device region of the motherboard substrate; Forming a reflective layer on the device region and the cutting region of the motherboard substrate, wherein the reflective layer is provided with a plurality of hollow areas along the direction perpendicular to the motherboard substrate, the interlayer dielectric layer is at least positioned between the motherboard substrate and the reflective layer, the orthographic projection of the part of the reflective layer positioned on the device region on the motherboard substrate overlaps with the orthographic projection of the interlayer dielectric layer on the motherboard substrate, and the part of the reflective layer positioned on the cutting region covers the cutting region of the motherboard substrate; binding a plurality of devices in the device region of the motherboard substrate, wherein the devices are positioned in the hollowed-out region; Cutting along a cutting line from the back surface of the motherboard substrate to obtain at least one array substrate, wherein the cutting line is positioned in the cutting area, and the back surface is the surface of the motherboard substrate away from the device; After the step of binding a plurality of devices in the device region of the motherboard substrate and before the step of dicing along dicing lines from the back surface of the motherboard substrate to obtain at least one array substrate, the method further comprises: forming an auxiliary reflecting part on the interlayer dielectric layer, wherein the auxiliary reflecting part is connected with the reflecting layer; the hollowed-out area exposes a partial area of the interlayer dielectric layer, the orthographic projection of the first reflecting part on the substrate is positioned in the hollowed-out area, and the first reflecting part is in direct contact with the interlayer dielectric layer; the second reflecting part is in direct contact with the surface of the reflecting layer, which is far away from the substrate, and the orthographic projection of the second reflecting part on the substrate is overlapped with the orthographic projection of the reflecting layer on the substrate; The array substrate further comprises a plurality of packaging units corresponding to the devices, orthographic projection of the packaging units on the substrate covers orthographic projection of the devices on the substrate, and orthographic projection of the packaging units on the substrate is overlapped with orthographic projection portions of the reflecting layers on the substrate.
14. The method for manufacturing an array substrate according to claim 13, wherein after the step of cutting along a dicing line from the back surface of the motherboard substrate to obtain at least one array substrate, the method further comprises: and grinding the edge of the array substrate by adopting a vertical grinding process.
15. The method for manufacturing an array substrate according to claim 14, wherein the step of polishing the edge of the array substrate using a vertical polishing process comprises: And simultaneously grinding the side surface of the substrate of the array substrate and the side surface of the reflecting layer in the direction perpendicular to the array substrate, wherein the side surface of the substrate and the side surface of the reflecting layer are coplanar.
16. The method of manufacturing an array substrate according to claim 13, wherein the step of forming a reflective layer on the device region and the dicing region of the motherboard substrate comprises: Forming a first reflection sub-layer, wherein orthographic projection of the first reflection sub-layer on the mother board substrate is positioned in the device area and the cutting area; Forming a second reflection sub-layer, wherein orthographic projection of the second reflection sub-layer on the mother board substrate is positioned in the device region; or forming a first reflection sub-layer, wherein orthographic projection of the first reflection sub-layer on the mother board substrate is positioned in the device area and the cutting area; and forming a second reflection sub-layer, wherein the orthographic projection of the second reflection sub-layer on the mother board substrate is positioned in the device area and the cutting area.

Description

Array substrate, preparation method thereof, light-emitting device and spliced display device Technical Field The application relates to the technical field of display, in particular to an array substrate, a preparation method thereof, a light-emitting device and a spliced display device. Background With the rapid development of display technology, display products of Mini LEDs (MINI LIGHT EMITTING Diode) and Micro LEDs (Micro LIGHT EMITTING Diode) are attracting attention. One of the advantages of Micro/mini LED display products is that the Micro/mini LED display products can be spliced in a large area, namely, a plurality of array substrates are used for splicing, so that display products with oversized size are obtained. Disclosure of Invention The embodiment of the application provides an array substrate, a preparation method thereof, a light-emitting device and a spliced display device, wherein the peripheral area of the array substrate can reflect light, so that the problem of large optical brightness difference of different areas of the array substrate is solved, and the display effect of the spliced display device prepared by the array substrate is improved. In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme: In one aspect, an array substrate is provided, including: A device region; a peripheral region adjacent to the device region; The device region and the peripheral region each comprise a substrate and a reflective layer on the substrate; the device region also comprises an interlayer dielectric layer and a plurality of devices, wherein the interlayer dielectric layer is at least positioned between the substrate and the reflecting layer, the reflecting layer is provided with a plurality of hollowed-out areas along the direction vertical to the substrate, and the devices are positioned in the hollowed-out areas; The device comprises a substrate, a reflection layer, an interlayer dielectric layer, a substrate, a peripheral region, a light-emitting device, a substrate, a light-emitting device and an array substrate, wherein the front projection of the reflection layer on the substrate in the part of the device region overlaps with the front projection of the interlayer dielectric layer on the substrate, the part of the reflection layer in the peripheral region covers the part of the substrate in the peripheral region, the outline of the substrate is consistent with the outline of the peripheral region of the array substrate, and the device at least comprises the light-emitting device. In some embodiments of the application, the reflective layer comprises a first reflective sub-layer and a second reflective sub-layer, the second reflective sub-layer being located on a side of the first reflective sub-layer remote from the substrate; The orthographic projection of the part of the first reflecting sub-layer, which is positioned in the device region, on the substrate is overlapped with the orthographic projection part of the interlayer dielectric layer on the substrate, and the part of the substrate, which is positioned in the peripheral region, is also covered by the first reflecting sub-layer; the orthographic projection of the second reflective sub-layer on the substrate is located within the orthographic projection of the first reflective sub-layer on the substrate. In some embodiments of the application, the orthographic projection of the second reflective sub-layer on the substrate is located in the device region; the orthographic projection of the second reflecting sub-layer on the substrate and the orthographic projection of the part of the first reflecting sub-layer, which is positioned in the peripheral area, on the substrate are not overlapped with each other. In some embodiments of the application, the orthographic projection of the second reflective sub-layer on the substrate is located at the peripheral region and the device region; the orthographic projection of the part of the second reflecting sub-layer positioned in the peripheral area on the substrate is overlapped with the orthographic projection of the part of the first reflecting sub-layer positioned in the peripheral area on the substrate. In some embodiments of the application, the thicknesses of the first and second reflective sublayers are the same in a direction perpendicular to the substrate. In some embodiments of the present application, the array substrate further includes an auxiliary reflection part, the auxiliary reflection part is located on the interlayer dielectric layer, and the auxiliary reflection part is connected with the reflection layer. In some embodiments of the application, the auxiliary reflecting portion includes a first reflecting portion and a second reflecting portion, the first reflecting portion and the second reflecting portion being of unitary construction; The hollowed-out area exposes a partial area of the interlayer dielectric l