CN-115700052-B - Display substrate, manufacturing method thereof and display device

CN115700052BCN 115700052 BCN115700052 BCN 115700052BCN-115700052-B

Abstract

The embodiment of the disclosure discloses a display substrate, a manufacturing method thereof and a display device, wherein the display substrate comprises a substrate and at least one layer of wiring layer, wherein the substrate is provided with a wiring area, the at least one layer of wiring layer is positioned on the substrate, each layer of wiring layer comprises a plurality of first wires and second wires which are arranged at intervals by adopting different patterning technologies, at least part of the first wires and the second wires are arranged adjacently, and the distance between the first wires and the second wires which are arranged adjacently is smaller than 2um.

Inventors

XU YUANJIE
WANG BENLIAN
ZHOU ZHENLI
REN ZHIMING
YANG XIAOFENG
WANG ZHEN
LU ZHONG
DU LILI
JIANG DONGHUA

Assignees

京东方科技集团股份有限公司
成都京东方光电科技有限公司

Dates

Publication Date: 20260505
Application Date: 20210527

Claims (20)

1. A display substrate, comprising: A substrate having a trace region; At least one layer of wiring layer is positioned on the substrate, the at least one layer of wiring layer comprises a plurality of first wirings and second wirings which are arranged at intervals by adopting different patterning technologies, at least part of the first wirings and the second wirings are arranged adjacently, and the distance between the first wirings and the second wirings which are arranged adjacently is smaller than 2um; The first wiring is made of p-ITO, the second wiring is made of a-ITO, crystal grains of the p-ITO are larger than those of the a-ITO, crystal boundaries of the p-ITO are smaller than those of the a-ITO, and resistance of the p-ITO is smaller than that of the a-ITO; Or the material of the first wire is a-ITO, and the material of the second wire comprises at least one of doping a-Si, IZO, IGZO; Or the material of the first wire is a-ITO, the second wire comprises a first sub-wire arranged on the substrate and a second sub-wire arranged on one side of the first sub-wire, which is away from the substrate, the first sub-wire and the second sub-wire are consistent in pattern and approximately overlap, the material of the first sub-wire is a-ITO, and the material of the second sub-wire comprises at least one of doping a-Si, IZO, IGZO.
2. The display substrate of claim 1, wherein the first and second traces of at least one of the trace layers are alternately spaced apart.
3. The display substrate of claim 1, comprising a display region and a bezel region, the display region comprising a first display region and a second display region, the first display region having a light transmittance that is greater than a light transmittance of the second display region; The first display area comprises a plurality of sub-pixels distributed in an array, the sub-pixels comprise a light emitting device and pixel circuits, the pixel circuits are positioned in the frame area adjacent to the first display area, or the second display area is provided with a transition area adjacent to the first display area, and the pixel circuits are positioned in the transition area, or the pixel circuits are distributed in the second display area; the wiring area is at least partially positioned in the first display area, and the wiring layer is positioned between the anode of the light emitting device and the pixel circuit; The first wiring is used for electrically connecting the corresponding light emitting device and the pixel circuit, and the second wiring is used for electrically connecting the corresponding light emitting device and the pixel circuit.
4. The display substrate according to claim 3, further comprising a flat layer on a side of the trace layer facing away from the base, wherein a first via hole is formed in the flat layer at a position corresponding to each of the first trace and the second trace, and an anode of the light emitting device is electrically connected to the first trace and the second trace through the corresponding first via hole.
5. The display substrate of claim 1, comprising a display region including a plurality of signal lines and a bezel region including the trace region; the first wire is used for being electrically connected with the corresponding signal wire, and the second wire is used for being electrically connected with the corresponding signal wire.
6. The display substrate according to claim 5, wherein the display substrate comprises a gate metal layer and a source-drain metal layer which are sequentially formed on the base, and the wiring layer is positioned on the gate metal layer and/or the source-drain metal layer.
7. The display substrate according to claim 1, wherein a distance between the first and second wirings adjacently disposed is 0.15um to 0.35um, a line width of the first wiring is less than or equal to 2um, and a line width of the second wiring is less than or equal to 2um.
8. The display substrate according to claim 1, wherein the number of the wiring layers is multiple, and each layer is arranged in an insulating manner between the wiring layers.
9. The display substrate of claim 8, wherein orthographic projections of each of the trace layers on the base are independently distributed.
10. A manufacturing method of a display substrate comprises the following steps: providing a substrate, wherein the substrate is provided with a wiring area; Forming at least one layer of wiring layer in a wiring area of the substrate, and patterning the corresponding wiring area of each wiring layer by adopting different patterning processes to obtain first wirings and second wirings which are arranged at intervals, wherein at least part of the first wirings and the second wirings are arranged adjacently, and the distance between the first wirings and the second wirings which are arranged adjacently is smaller than 2um; The first wiring is made of p-ITO, the second wiring is made of a-ITO, crystal grains of the p-ITO are larger than those of the a-ITO, crystal boundaries of the p-ITO are smaller than those of the a-ITO, and resistance of the p-ITO is smaller than that of the a-ITO; Or the material of the first wire is a-ITO, and the material of the second wire comprises at least one of doping a-Si, IZO, IGZO; Or the material of the first wire is a-ITO, the second wire comprises a first sub-wire arranged on the substrate and a second sub-wire arranged on one side of the first sub-wire, which is away from the substrate, the first sub-wire and the second sub-wire are consistent in pattern and approximately overlap, the material of the first sub-wire is a-ITO, and the material of the second sub-wire comprises at least one of doping a-Si, IZO, IGZO.
11. The method of claim 10, wherein the patterning of the first trace and the second trace in the trace area corresponding to each trace layer by using different patterning processes includes: Depositing a first conductive layer in a wiring area of the substrate; Annealing the first conductive layer; Coating a first photoresist on one side of the annealed first conductive layer, which is away from the substrate, and exposing and developing the first photoresist to form a patterned first photoresist layer; Etching the annealed first conductive layer by using the first photoresist layer as a mask and adopting a first etching material, wherein a plurality of first wirings are formed on the annealed first conductive layer at intervals; depositing a second conductive layer on one side of the plurality of first wires, which is away from the substrate, wherein the material of the second conductive layer is the same as that of the first conductive layer before annealing; Coating a second photoresist on one side of the second conductive layer, which is away from the substrate, and exposing and developing the second photoresist, forming a second photoresist complete removal area in an area corresponding to the first wiring, and forming a second photoresist retention area in an area corresponding to an area between adjacent first wirings so as to form a patterned second photoresist layer; and etching the second conductive layer by using the second photoresist layer as a mask and adopting a second etching material to form second wiring between each two adjacent first wirings.
12. The method of claim 10, wherein the patterning of the first trace and the second trace in the trace area corresponding to each trace layer by using different patterning processes includes: Depositing a first conductive layer in a wiring area of the substrate; Coating a first photoresist on one side of the first conductive layer, which is away from the substrate, and exposing and developing the first photoresist to form a patterned first photoresist layer; Etching the first conductive layer by using the first photoresist layer as a mask and adopting a second etching material to form a plurality of first wirings which are arranged at intervals on the first conductive layer; annealing the first conductive layer formed with the plurality of first wires; depositing a second conductive layer on one side of the annealed first conductive layer away from the substrate, wherein the material of the second conductive layer is different from the material type of the annealed first conductive layer; Coating a second photoresist on one side of the second conductive layer, which is away from the substrate, and exposing and developing the second photoresist, forming a second photoresist complete removal area in an area corresponding to the first wiring, and forming a second photoresist retention area in an area corresponding to an area between adjacent first wirings so as to form a patterned second photoresist layer; and etching the second conductive layer by using the second photoresist layer as a mask and adopting the second etching material to form second wiring between each two adjacent first wirings.
13. The method of claim 11 or 12, wherein the display substrate comprises a display region and a frame region, the display region comprises a first display region and a second display region, the first display region has a light transmittance greater than that of the second display region, the first display region comprises a plurality of sub-pixels distributed in an array, the sub-pixels comprise light emitting devices and pixel circuits, the pixel circuits are positioned in the frame region adjacent to the first display region, or the second display region has a transition region adjacent to the first display region, the pixel circuits are positioned in the transition region, or the pixel circuits are distributed in the second display region, the trace region is positioned at least partially in the first display region, and the trace layer is positioned between an anode of the light emitting device and the pixel circuits, the first trace is used for electrically connecting the corresponding light emitting device and the pixel circuit, the second trace is used for electrically connecting the corresponding light emitting device and the pixel circuit, The annealed material of the first conductive layer is p-ITO, the material of the second conductive layer is a-ITO, the p-ITO is annealed at a high temperature, the a-ITO is annealed at normal temperature, the crystal grains of the p-ITO are larger than those of the a-ITO, the crystal grain boundary of the p-ITO is smaller than that of the a-ITO, and the resistance of the p-ITO is smaller than that of the a-ITO.
14. The manufacturing method of claim 11 or 12, wherein the manufacturing method comprises a display area and a frame area, wherein the display area comprises a plurality of signal wires, the frame area comprises the wiring area, the first wiring is used for electrically connecting the corresponding signal wires, and the second wiring is used for electrically connecting the corresponding signal wires; The material of the second conductive layer and the material of the first conductive layer before annealing are the same metal material.
15. The method of claim 10, wherein the patterning of the first trace and the second trace in the trace area corresponding to each trace layer by using different patterning processes includes: Depositing a first conductive layer in a wiring area of the substrate; Coating a first photoresist on one side of the first conductive layer, which is away from the substrate, and exposing and developing the first photoresist to form a patterned first photoresist layer; Etching the first conductive layer by using the first photoresist layer as a mask and adopting a second etching material to form a plurality of first wirings which are arranged at intervals on the first conductive layer; Depositing a second conductive layer on one side of the first conductive layer, which is provided with the plurality of first wires and is away from the substrate, wherein the material of the second conductive layer is different from that of the first conductive layer; Coating a second photoresist on one side of the second conductive layer, which is away from the substrate, and exposing and developing the second photoresist, forming a second photoresist complete removal area in an area corresponding to the first wiring, and forming a second photoresist retention area in an area corresponding to an area between adjacent first wirings so as to form a patterned second photoresist layer; and etching the second conductive layer by using the second photoresist layer as a mask and adopting a first etching material to form a second wiring between each two adjacent first wirings, wherein the second etching material is different from the first etching material.
16. The method of claim 10, wherein the patterning of the first trace and the second trace in the trace area corresponding to each trace layer by using different patterning processes includes: Depositing a first conductive layer in a wiring area of the substrate; depositing a second conductive layer on one side of the first conductive layer away from the substrate, wherein the material of the second conductive layer is different from the material of the first conductive layer; Coating a first photoresist on one side of the second conductive layer, which is away from the substrate, and exposing and developing the first photoresist to form a first photoresist complete removal area and a first photoresist retention area which are alternately arranged to form a patterned first photoresist layer; etching the second conductive layer by using the first photoresist layer as a mask and adopting a first etching material, and forming a plurality of second sub-wirings which are arranged at intervals on the second conductive layer; Depositing a second photoresist on one side of the second conductive layer, which is provided with the plurality of second sub-wires and is away from the substrate, exposing and developing the second photoresist, forming a second photoresist complete removal area in an area corresponding to the second sub-wires, forming a second photoresist reserved area in an area corresponding to an adjacent second sub-wire, and forming a patterned second photoresist layer by a preset gap between the second photoresist reserved area and the second sub-wire; And etching the first conductive layer by using a second etching material with the second photoresist layer as a mask to form first wirings positioned between every two adjacent second sub-wirings and first sub-wirings positioned below the second sub-wirings, wherein the first sub-wirings and the second sub-wirings form the second wirings, and the second etching material is different from the first etching material.
17. The method of claim 15 or 16, wherein the display substrate comprises a display region and a frame region, the display region comprises a first display region and a second display region, the first display region has a light transmittance greater than that of the second display region, the first display region comprises a plurality of sub-pixels distributed in an array, the sub-pixels comprise light emitting devices and pixel circuits, the pixel circuits are positioned in the frame region adjacent to the first display region, or the second display region has a transition region adjacent to the first display region, the pixel circuits are positioned in the transition region, or the pixel circuits are distributed in the second display region, the trace region is positioned at least partially in the first display region, and the trace layer is positioned between an anode of the light emitting device and the pixel circuits, the first trace is used for electrically connecting the corresponding light emitting device and the pixel circuit, the second trace is used for electrically connecting the corresponding light emitting device and the pixel circuit, The material of the first conductive layer is a-ITO, and the material of the second conductive layer comprises at least one of doped a-Si, IZO, IGZO.
18. The method of claim 15 or 16, wherein the display substrate comprises a display region and a frame region, the display region comprises a plurality of signal lines, the frame region comprises the wiring region, the first wiring is used for electrically connecting the corresponding signal lines, the second wiring is used for electrically connecting the corresponding signal lines, wherein, The material of the first conductive layer and the material of the second conductive layer are different metal materials.
19. The method of manufacturing of claim 17, further comprising: depositing a flat layer on one side of the wiring layer away from the substrate; patterning the flat layer to form first through holes corresponding to the first wires and the second wires respectively; And forming a plurality of anodes on one side of the flat layer, which is provided with the first via holes and is away from the substrate, wherein each anode is electrically connected with the first wire or the second wire through the corresponding first via hole.
20. The method of any of claims 11, 15, 16, wherein the first etching material comprises nitric acid.

Description

Display substrate, manufacturing method thereof and display device Technical Field The disclosure relates to the technical field of display, in particular to a display substrate, a manufacturing method thereof and a display device. Background With the high-speed development of smart phones, not only is the appearance of the smart phone attractive, but also more excellent visual experience is brought to the mobile phone user. Each large manufacturer starts to increase the screen duty ratio on the smart phone, so that the comprehensive screen becomes a new competitive point of the smart phone. With the development of the comprehensive screen, the improvement demands on performance and functions are increasing, and the under-screen camera can bring impact feeling on vision and use experience to a certain extent on the premise of not influencing the high screen ratio. Disclosure of Invention In one aspect, an embodiment of the present disclosure provides a display substrate, including: A substrate having a trace region; At least one layer of wiring layer is located on the substrate, at least one layer of wiring layer is in the wiring area includes a plurality of first wires and second wires that adopt different structure drawing technologies to obtain the interval setting, at least part first wires with the second wires are adjacent to be set up, and the adjacent setting first wires with distance between the second wires is less than 2um. Optionally, in the foregoing display substrate provided by the embodiments of the present disclosure, the first wires and the second wires of at least one layer of the wire layer are alternately arranged at intervals. Optionally, in the foregoing display substrate provided by the embodiments of the present disclosure, the display substrate includes a display area and a frame area, where the display area includes a first display area and a second display area, and a light transmittance of the first display area is greater than a light transmittance of the second display area; The first display area comprises a plurality of sub-pixels distributed in an array, the sub-pixels comprise a light emitting device and pixel circuits, the pixel circuits are positioned in the frame area adjacent to the first display area, or the second display area is provided with a transition area adjacent to the first display area, and the pixel circuits are positioned in the transition area, or the pixel circuits are distributed in the second display area; the wiring area is at least partially positioned in the first display area, and the wiring layer is positioned between the anode of the light emitting device and the pixel circuit; The first wiring is used for electrically connecting the corresponding light emitting device and the pixel circuit, and the second wiring is used for electrically connecting the corresponding light emitting device and the pixel circuit. Optionally, in the display substrate provided by the embodiment of the disclosure, the material of the first trace is p-ITO, and the material of the second trace is a-ITO, where grains of the p-ITO are larger than grains of the a-ITO, grain boundaries of the p-ITO are smaller than grain boundaries of the a-ITO, and resistance of the p-ITO is smaller than resistance of the a-ITO. Optionally, in the display substrate provided by the embodiment of the present disclosure, a material of the first trace is a-ITO, and a material of the second trace includes at least one of doped a-Si, IZO, IGZO. Optionally, in the foregoing display substrate provided by the embodiment of the present disclosure, the material of the first trace is a-ITO, the second trace includes a first sub-trace disposed on the substrate and a second sub-trace disposed on a side of the first sub-trace facing away from the substrate, the first sub-trace and the second sub-trace are consistent and substantially overlap in pattern, the material of the first sub-trace is a-ITO, and the material of the second sub-trace includes at least one of doped a-Si, IZO, IGZO. Optionally, in the foregoing display substrate provided by the embodiment of the present disclosure, the display substrate further includes a flat layer located on a side of the wiring layer away from the substrate, a first via hole is located in the flat layer at a position corresponding to each of the first wiring and the second wiring, and an anode of the light emitting device is electrically connected to the first wiring and the second wiring through the corresponding first via hole. Optionally, in the foregoing display substrate provided by the embodiments of the present disclosure, the display substrate includes a display area and a frame area, where the display area includes a plurality of signal lines, and the frame area includes the routing area; the first wire is used for being electrically connected with the corresponding signal wire, and the second wire is used for being electrically connected with the correspo