CN-115707228-B - Dynamic random access memory and manufacturing method thereof

Abstract

The invention provides a dynamic random access memory and a manufacturing method thereof. The DRAM includes a plurality of bit line contact structures, a plurality of bit line structures, a plurality of first insulating structures, a capacitor contact structure, a first connection pad, a second insulating structure, and a capacitor structure. The bit line structure extends along a first direction. The first insulating structure extends along a second direction intersecting the first direction. The capacitor contact structure is located between the two bit line structures and the two first insulating structures. The first connection pad is formed on the capacitor contact structure. The second insulating structure surrounds the first connecting pad, and the top width of the second insulating structure is larger than the bottom width. The capacitor structure is formed on the first connection pad and is electrically connected with the first connection pad.

Inventors

• Chen Huangnan

Assignees

• 华邦电子股份有限公司

Dates

Publication Date

20260505

Application Date

20210714

Claims (16)

1. 1. A dynamic random access memory, comprising: A plurality of bit line contact structures formed on a substrate; a plurality of bit line structures formed on the bit line contact structures and extending along a first direction; A plurality of first insulating structures formed on the substrate and extending along a second direction intersecting the first direction; A capacitor contact structure formed on the substrate and located between the adjacent bit line structure and the adjacent first insulating structure; A first connection pad formed on the capacitor contact structure; a second insulating structure surrounding the first connecting pad and having a top width greater than a bottom width, and And the capacitor structure is formed on the first connecting pad and is electrically connected with the first connecting pad, wherein a top surface of the second insulating structure is flush with a top surface of the first connecting pad and a top surface of the bit line structure.
2. 2. The dynamic random access memory of claim 1, wherein the second insulating structure comprises: a first portion extending upward from a top surface of the capacitor contact structure, wherein the first portion has a width that gradually narrows downward, and A second portion extending downward from the top surface of the first connection pad, wherein the second portion has a width that gradually narrows downward, wherein the top surface of the second insulating structure has a first width W1, wherein a surface of the first portion of the second insulating structure has a maximum distance W2 from a sidewall surface of the bit line structure, and wherein a ratio (W1/W2) of the first width W1 to the maximum distance W2 is 1.5-10.0.
3. 3. The dynamic random access memory of claim 2, wherein the first portion comprises a first insulating material, the second portion comprises a second insulating material, and the second insulating material is different from the first insulating material.
4. 4. The dynamic random access memory of claim 2, wherein the first portion comprises an air gap and the second portion comprises an insulating material.
5. 5. The dynamic random access memory of claim 2, wherein the first portion and the second portion comprise the same insulating material.
6. 6. The dynamic random access memory of claim 2, wherein said second insulating structure has a first height H1, said second portion has a minimum thickness H2, and wherein a ratio (H1/H2) of said first height H1 to said minimum thickness H2 is 1.5-10.0.
7. 7. The dynamic random access memory of claim 2, wherein said second insulating structure further comprises a third portion between said first portion and said second portion, said first portion comprising a first insulating material, said second portion comprising a second insulating material, said third portion comprising an air gap, and said second insulating material being different from said first insulating material.
8. 8. The dynamic random access memory of claim 1, wherein the bit line structure comprises: A conductive structure formed on the bit line contact structure; an insulating cap layer formed over the conductive structure; An insulating spacer between the conductive structure and the capacitive contact structure, and comprising: a first spacer layer formed on a sidewall of the insulating cap layer and a sidewall of the conductive structure; A second spacer layer formed on the first spacer layer, wherein a top surface of the second spacer layer is lower than a top surface of the first spacer layer, and A third spacer layer formed on the second spacer layer, wherein a top surface of the third spacer layer is lower than the top surface of the first spacer layer.
9. 9. The dynamic random access memory of claim 1, wherein a width of a bottom surface of the first connection pad is greater than a width of a top surface of the first connection pad, and a ratio of a width of an interface of a lower portion and an upper portion of the first connection pad to a width of the top surface of the first connection pad is 1.1-2.5.
10. 10. A method of manufacturing a dynamic random access memory, comprising: Forming a plurality of bit line contact structures on a substrate; Forming a plurality of bit line structures on the bit line contact structures, wherein each bit line structure extends along a first direction; Forming a plurality of first insulating structures on the substrate, wherein each first insulating structure extends along a second direction intersecting the first direction; Forming a capacitor contact structure on the substrate, wherein the capacitor contact structure is located between the adjacent bit line structure and the adjacent first insulating structure; Forming a first connection pad on the capacitor contact structure; Forming a second insulating structure surrounding the first connecting pad, wherein the second insulating structure has a top width greater than a bottom width, and A capacitor structure is formed on and electrically connected to the first connection pad, wherein a top surface of the second insulating structure is flush with a top surface of the first connection pad and a top surface of the bit line structure.
11. 11. The method of claim 10, wherein forming the second insulating structure and forming the first connection pad comprises: Forming a first material layer with non-uniform thickness on the bit line structure and the capacitor contact structure, wherein the first material layer comprises a first insulating material; Performing a first etching process to partially remove the first material layer and expose a top surface of the capacitor contact structure; Depositing a conductive material on the first material layer and the capacitor contact structure; performing a planarization process to make a top surface of the first material layer coplanar with a top surface of the conductive material, wherein the conductive material forms the first connection pad after the planarization process; performing a second etching process to remove a portion of the first material layer and form a recess adjacent to the first connection pad, and Forming a second insulating material in the recess, wherein the second insulating material is different from the first insulating material, Wherein a top surface of the second insulating structure is flush with a top surface of the first connection pad.
12. 12. The method of claim 11, wherein the recess is formed by removing an overhanging portion of the first material layer through the first etching process.
13. 13. The method of claim 11, wherein the second insulating material fills the recess and the remaining first material layer and the second insulating material form the second insulating structure.
14. 14. The method of claim 11, wherein the second insulating material does not completely fill the recess to form an air gap in the recess between the first material layer and the second insulating material, and wherein the remaining first material layer, second insulating material and air gap form the second insulating structure.
15. 15. The method of claim 10, wherein forming the second insulating structure and forming the first connection pad comprises: Forming a first material layer with non-uniform thickness on the bit line structure and the capacitor contact structure; Performing a first etching process to partially remove the first material layer and expose a top surface of the capacitor contact structure; Depositing a conductive material on the first material layer and the capacitor contact structure; Performing a planarization process to make a top surface of the first material layer coplanar with a top surface of the conductive material; after the planarization process, the conductive material forms the first connection pad, and the first connection pad is in direct contact with the capacitance contact structure; performing a second etching process to completely remove the first material layer and form an opening exposing the sidewall of the first connection pad, and The second insulating structure is formed in the opening, wherein the material of the second insulating structure is different from the material of the first material layer.
16. 16. The method of claim 15, wherein forming the second insulating structure in the opening comprises forming an insulating material that does not completely fill the opening to form an air gap in the opening below the insulating material, and wherein the insulating material and the air gap form the second insulating structure.

Description

Dynamic random access memory and manufacturing method thereof Technical Field The present invention relates to a memory device, and more particularly, to a dynamic random access memory and a method for fabricating the same. Background With the trend of miniaturization of electronic products, there is a demand for miniaturization of memory devices. However, with the miniaturization of memory devices, it becomes more difficult to improve the performance and yield of memory devices. For example, in a dynamic random access memory (dynamic random access memory, DRAM), the bit line structure has sidewall spacers formed of nitride/oxide/nitride. In wet etching, the top of the oxide in the sidewall spacers is often damaged, resulting in thinning or even complete removal of the top of the sidewall spacers (i.e., the top surface of the sidewall spacers is lower than the top surface of the cap layer over the conductive structure) because the oxide is less resistant to wet etching than the nitride. If the top of the sidewall spacers of the bit line structure are completely removed, the top of the cap layer in the bit line structure may be exposed, resulting in the cap layer also being deformed (e.g., the cap layer having a rounded top surface), thereby resulting in the tops of the connection pads on both sides of the bit line structure becoming wider than desired. In other words, the distance between the tops of adjacent connection pads becomes closer. In this way, the risk of shorting the memory device is increased, thereby reducing the efficiency and yield of the product. As the memory device is miniaturized, the distance between adjacent connection pads is reduced, and thus, the problem of the short circuit becomes more serious. Disclosure of Invention The embodiment of the invention provides a dynamic random access memory and a manufacturing method thereof, which can reduce the risk of short circuit and are beneficial to miniaturization. An embodiment of the invention discloses a dynamic random access memory, which comprises a plurality of bit line contact structures, a plurality of first insulating structures, a capacitor contact structure, a first connecting pad, a second insulating structure and a capacitor structure, wherein the plurality of bit line contact structures are formed on a substrate, the plurality of bit line structures are formed on the plurality of bit line contact structures and extend along a first direction, the plurality of first insulating structures are formed on the substrate and extend along a second direction intersecting the first direction, the capacitor contact structure is positioned between the adjacent plurality of bit line structures and the adjacent plurality of first insulating structures, the first connecting pad is formed on the capacitor contact structure, the second insulating structure surrounds the first connecting pad, and the top width of the second insulating structure is larger than the bottom width of the second insulating structure, and the capacitor structure is formed on the first connecting pad and is electrically connected with the first connecting pad. An embodiment of the invention discloses a manufacturing method of a dynamic random access memory, which comprises the steps of forming a plurality of bit line contact structures on a substrate, forming a plurality of bit line structures on the plurality of bit line contact structures, wherein each bit line structure extends along a first direction, forming a plurality of first insulating structures on the substrate, wherein each first insulating structure extends along a second direction intersecting the first direction, forming a capacitor contact structure between the adjacent plurality of bit line structures and the adjacent plurality of first insulating structures, forming a first connecting pad on the capacitor contact structure, forming a second insulating structure surrounding the first connecting pad, wherein the top width of the second insulating structure is larger than the bottom width, and forming a capacitor structure on the first connecting pad and electrically connected with the first connecting pad. In the DRAM and the method for manufacturing the same provided by the embodiment of the invention, the risk of short circuit can be reduced by forming the second insulation structure surrounding the first connection pad. Furthermore, the top width of the second insulation structure is larger than the bottom width, so that the first connection pad and the capacitor structure can have proper contact impedance, and parasitic capacitance between the bit line structure and the first connection pad is reduced. Thus, performance and yield can be improved. Drawings FIG. 1 is a schematic top view of a DRAM according to some embodiments of the present invention. Fig. 2A to 2G are schematic cross-sectional views of a DRAM according to an embodiment of the present invention, which are drawn along a cross-sectional