CN-115712387-B - Adjustable data protection scheme using artificial intelligence

Abstract

Apparatus and methods may involve implementing an adjustable data protection scheme using artificial intelligence. Implementing an adjustable data protection scheme may include receiving failure data for a plurality of memory devices and receiving an indication of a failure of a stripe of the plurality of memory devices based on the failure data. Based on fault data and the indication of the fault of the stripe of the plurality of memory devices, a data protection scheme adjustment for the memory devices may be generated. The data protection scheme adjustment may be received from an AI accelerator and may be implemented by a plurality of memory devices.

Inventors

• E. E. haltz
• N. Sobelanes
• J. A. de la Zelda
• B. Rivera
• B. J. Ford

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20220817

Priority Date

20210819

Claims (20)

1. 1. An apparatus, comprising: A plurality of memory devices implementing a data protection scheme; An artificial intelligence AI accelerator coupled to the plurality of memory devices; Wherein the AI accelerator is configured to: receiving failure data for the plurality of memory devices; receiving an indication of a failure of a stripe of the plurality of memory devices based on the failure data, and Generating data protection scheme adjustments for the plurality of memory devices based on fault data and the indication of the fault of the stripe of the plurality of memory devices; wherein the plurality of memory devices are configured to: Receiving the data protection scheme adjustment from the AI accelerator, and Implementing the data protection scheme adjustment, and Additional data protection scheme adjustments for a plurality of blocks of the plurality of memory devices are generated based on cycle counts of the plurality of blocks and based on original bit error rates of the plurality of blocks of the plurality of memory devices, Wherein the plurality of blocks have erase and program delays similar to erase and program delays corresponding to the fault data.
2. 2. The apparatus of claim 1, wherein the AI accelerator is further configured to receive an indication of a failure of a block of the plurality of memory devices.
3. 3. The apparatus of claim 1, wherein the AI accelerator is further configured to receive an indication of a failure of a word line of the plurality of memory devices.
4. 4. The apparatus of claim 1, wherein the plurality of memory devices configured to implement the data protection scheme adjustment are further configured to adjust a parity element to storage element ratio.
5. 5. The apparatus of claim 1, wherein the plurality of memory devices configured to implement the data protection scheme adjustment are further configured to avoid utilizing blocks of the plurality of memory devices.
6. 6. The apparatus of claim 1, wherein the plurality of memory devices configured to implement the data protection scheme adjustment are further configured to adjust a number of bits that each of a plurality of memory cells is capable of storing.
7. 7. The apparatus of claim 6, wherein the plurality of memory devices are configured to adjust the number of bits that each of the plurality of memory cells is capable of storing from a single level cell SLC to a multi-level cell MLC.
8. 8. The apparatus of claim 6, wherein the plurality of memory devices are configured to adjust the levels of the plurality of memory cells from a multi-level cell MLC to a single-level cell SLC.
9. 9. The device of claim 1, wherein the AI accelerator is further configured to utilize an artificial neural network ANN to generate the data protection scheme adjustment.
10. 10. The device of claim 1, wherein the AI accelerator configured to generate the data protection scheme adjustment is further configured to select the data protection scheme adjustment by comparing the fault data with a plurality of signatures including fault data using a table.
11. 11. The device of claim 1, wherein the AI accelerator is further configured to: providing data corresponding to the fault data to a cloud system for addition to a pool of faults, and Receiving additional data protection scheme adjustments corresponding to the pool of faults from the cloud system; The data protection scheme adjustment is generated for a failure that the plurality of memory devices have not experienced by selecting a data protection scheme adjustment from the additional data protection scheme adjustment.
12. 12. The apparatus of claim 1, wherein the failure data comprises latency data, read latency data, erasure latency data, and an original bit error rate RBER.
13. 13. A method, comprising: receiving a plurality of raw bit error rates RBER experienced by a time memory device prior to generating temperature data; receiving the temperature data of the memory device coupled to an artificial intelligence AI accelerator, the memory device implementing a data protection scheme during operation of the memory device; Generating, at the AI accelerator, a threshold temperature based on the plurality of RBER and previous temperature data; Receiving an indication of a failure of a stripe of the memory device; determining, at the AI accelerator, whether the temperature data indicates that a temperature corresponding to the temperature data is greater than the threshold temperature of the memory device; Generating a data protection scheme adjustment for the memory device at the AI accelerator based on the temperature data being greater than the threshold temperature and the indication of the failure of the stripe of the memory device, and The data protection scheme adjustment is implemented at the memory device.
14. 14. The method as recited in claim 13, further comprising: Receiving a different indication of no failure of the memory device, and Based on the temperature data and the different indications of the absence of faults of the memory device, different data protection scheme adjustments for the memory device are generated at the artificial intelligence AI accelerator.
15. 15. The method of claim 14, wherein the data protection scheme adjustment emphasizes data protection scheme coverage in the memory device and the different data protection scheme adjustment weakens independent NAND redundant array RAIN coverage in the memory device.
16. 16. An apparatus, comprising: a memory device implementing a data protection scheme; an artificial intelligence AI accelerator coupled to the memory device; Wherein the AI accelerator is configured to: Receiving an original bit error rate RBER of the memory device and during operation of the memory device; Receiving data corresponding to a pass or fail condition of the memory device, and Generating a data protection scheme adjustment for the memory device to extend a lifetime of the memory device based on the RBER and the data; Wherein the memory device is configured to implement the data protection scheme adjustment; Additional data protection scheme adjustments for a plurality of blocks of the memory device are generated based on cycle counts of the plurality of blocks and based on original bit error rates of the plurality of blocks of the memory device, Wherein the plurality of blocks have erase and program delays similar to erase and program delays corresponding to fault data.
17. 17. The apparatus of claim 16, wherein the AI accelerator is configured to receive the data corresponding to a pass or fail condition of a block or word line of the memory device.
18. 18. The apparatus of claim 16, wherein the AI accelerator is configured to generate the data protection scheme adjustment for a block or word line of the memory device.
19. 19. The device of claim 16, wherein the AI accelerator is further configured to: Generating an average margin to a fault condition of the memory device using the data corresponding to the fault condition and the RBER, and The data protection scheme adjustment is generated based on the average margin and the fault condition.
20. 20. A system, comprising: the AI accelerator is implemented in the cloud system; A plurality of memory devices implementing a data protection scheme; Wherein the AI accelerator is configured to: receiving manufacturing data and test data; receiving status data describing a status of the plurality of memory devices; receiving a fuse identification ID corresponding to at least one of the plurality of memory devices; Generating a data protection scheme adjustment for a memory cell corresponding to the fuse ID in response to receipt of the manufacturing data, the test data, and the status data, and Wherein the plurality of memory devices are configured to implement the data protection scheme adjustment for the memory cells corresponding to the fuse ID.

Description

Adjustable data protection scheme using artificial intelligence Technical Field The present disclosure relates generally to electronic memory systems and devices, and more particularly, to apparatus and methods associated with implementing an adjustable data protection scheme using Artificial Intelligence (AI). Background Memory devices are typically provided as internal semiconductor integrated circuit devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes Random Access Memory (RAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), and the like. Nonvolatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically Erasable Programmable ROM (EEPROM), erasable Programmable ROM (EPROM), and resistance variable memory such as Phase Change Random Access Memory (PCRAM), resistive Random Access Memory (RRAM), magnetoresistive Random Access Memory (MRAM), and the like. Memory is also used as both volatile and nonvolatile data storage for a wide range of electronic applications. Including but not limited to personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players, such as MP3 players, movie players, and other electronic devices. The memory cells may be arranged in an array, where the array is used in a memory device. Various data protection schemes may be used to ensure data integrity within the memory. Disclosure of Invention In one aspect, the present disclosure provides an apparatus comprising a plurality of memory devices implementing a data protection scheme, an Artificial Intelligence (AI) accelerator coupled to the plurality of memory devices, wherein the AI accelerator is configured to receive failure data for the plurality of memory devices, receive an indication of a failure of a stripe of the plurality of memory devices based on the failure data, and generate a data protection scheme adjustment for the plurality of memory devices based on the failure data and the indication of the failure of the stripe of the plurality of memory devices, wherein the plurality of memory devices are configured to receive the data protection scheme adjustment from the AI accelerator, and implement the data protection scheme adjustment. In another aspect, the present disclosure further provides a method comprising receiving temperature data of a memory device coupled to an Artificial Intelligence (AI) accelerator, the memory device implementing a data protection scheme during operation of the memory device, receiving an indication of a failure of a stripe of the memory device, generating a data protection scheme adjustment for the memory device at the AI accelerator based on the temperature data and the indication of the failure of the stripe of the memory device, and implementing the data protection scheme adjustment at the memory device. In yet another aspect, the present disclosure further provides an apparatus comprising a memory device implementing a data protection scheme, an Artificial Intelligence (AI) accelerator coupled to the memory device, wherein the AI accelerator is configured to receive a Raw Bit Error Rate (RBER) of the memory device and during operation of the memory device, receive data corresponding to a pass or fail condition of the memory device, and generate a data protection scheme adjustment for the memory device based on the RBER and the data to extend a lifetime of the memory device, wherein the memory device is configured to implement the data protection scheme adjustment. In yet another aspect, the present disclosure further provides a system including an AI accelerator implemented in a cloud system, a plurality of memory devices implementing a data protection scheme, wherein the AI accelerator is configured to receive manufacturing data and test data, receive status data describing a status of the plurality of memory devices, receive a fuse Identification (ID) corresponding to at least one of the plurality of memory devices, generate a data protection scheme adjustment for a memory cell corresponding to the fuse ID in response to the receipt of the manufacturing data, the test data, and the status data, and wherein the plurality of memory devices are configured to implement the data protection scheme adjustment for the memory cell corresponding to the fuse ID. Drawings Fig. 1 is a block diagram of a device in the form of a computing system including a memory subsystem according to several embodiments of the present disclosure. Fig. 2 illustrates a block diagram of RAIN adjustment via a cloud system, according to several embodiments of the present disclosure. Fig. 3 illustrates a block diagram of a memory subsystem for implementing RAIN adjustment based on er