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CN-115713955-B - 2D1R array structure and preparation method thereof

CN115713955BCN 115713955 BCN115713955 BCN 115713955BCN-115713955-B

Abstract

The invention provides a 2D1R array structure and a preparation method thereof, wherein the 2D1R array structure comprises m word lines, m reset lines and n bit lines which are transversely arranged and are in one-to-one correspondence, n bit lines which are longitudinally arranged, m and n are integers, m is more than or equal to 2, n is more than or equal to 2, storage units are arranged at intersections of the word lines and the bit lines, each storage unit comprises a first diode, a second diode and a resistor, one end of the resistor is connected with the corresponding bit line, the other end of the resistor is connected with the positive electrode of the first diode and the negative electrode of the second diode respectively, the negative electrode of the first diode is connected with the corresponding word line, and the positive electrode of the second diode is connected with the corresponding reset line. The 2D1R array structure provided by the invention can solve the problems that the isolation performance between wells in the existing 2D1R array structure is poor and larger IR drop is easy to generate.

Inventors

  • CAO HENG
  • QIU SHENGFEN

Assignees

  • 昕原半导体(上海)有限公司

Dates

Publication Date
20260508
Application Date
20221021

Claims (9)

  1. 1. A2D 1R array structure is characterized by comprising m word lines, m reset lines and n bit lines which are transversely arranged and are in one-to-one correspondence, wherein m and n are integers, m is more than or equal to 2, n is more than or equal to 2, and The memory cell comprises a first diode, a second diode and a resistor, wherein one end of the resistor is connected with a corresponding bit line, the other end of the resistor is respectively connected with the positive electrode of the first diode and the negative electrode of the second diode, the negative electrode of the first diode is connected with a corresponding word line, the positive electrode of the second diode is connected with a corresponding reset line, the memory cell is a 2D1R cell, and the 2D1R cell is prepared based on the following process: Forming alternately arranged n-well regions and p-well regions by means of ion implantation; forming a deep trench region at the junction of the n-well region and the p-well region through an etching process, and arranging shallow trench regions in each n-well region and each p-well region through the etching process; Processing the deep trench region and the shallow trench region through filling and grinding processes so as to separate adjacent n-well regions from p-well regions through the deep trench region, and forming separated active regions in each n-well region and each p-well region through the shallow trench region; processing each active region by means of ion implantation to form an n-type active region and a p-type active region in each n-well region and each p-well region; Intercepting corresponding n-type active regions, p-type active regions, deep groove regions and shallow grooves, and connecting the n-type active regions, the p-type active regions, the deep groove regions and the shallow grooves with resistors in a preset resistor matrix to form a 2D1R unit, wherein for each n-well region, one n-type active region is arranged every two p-type active regions at intervals and is used as an n+ leading-out terminal, and for each p-well region, one p-type active region is arranged every two n-type active regions at intervals and is used as a p+ leading-out terminal.
  2. 2. The 2D1R array structure of claim 1, In the course of the reading process, For the memory cells which are not selected in the 2D1R array structure, the bit line is at 0V voltage, the word line is at 0V voltage, and the reset line is at 0V voltage; wherein, the vrd is more than or equal to 0.3V and less than or equal to 1V.
  3. 3. The 2D1R array structure of claim 1, During the course of the writing process, For the memory cells selected in the 2D1R array structure, the bit line is at the Vset voltage, the word line is at the 0V voltage, and the reset line is at the 0V voltage; Wherein Vset is more than or equal to 2.0V and less than or equal to 3.5V.
  4. 4. The 2D1R array structure of claim 1, In the course of the reset procedure, the reset, For the memory cells selected in the 2D1R array structure, the bit line is at 0V voltage, the word line is at Vreset voltage, and the reset line is at Vreset voltage; for unselected memory cells in the 2D1R array structure, the bit line is set at Vreset voltage, the word line is set at Vreset voltage, and the reset line is set at 0V voltage; wherein, the vreset is less than or equal to 1.5V and less than or equal to 3.5V.
  5. 5. A method of producing a 2D1R array according to any one of claims 1 to 4, comprising: Forming alternately arranged n-well regions and p-well regions by means of ion implantation; forming a deep trench region at the junction of the n-well region and the p-well region through an etching process, and arranging shallow trench regions in each n-well region and each p-well region through the etching process; Processing the deep trench region and the shallow trench region through filling and grinding processes so as to separate adjacent n-well regions from p-well regions through the deep trench region, and forming separated active regions in each n-well region and each p-well region through the shallow trench region; processing each active region by means of ion implantation to form an n-type active region and a p-type active region in each n-well region and each p-well region; Intercepting corresponding n-type active regions, p-type active regions, deep trench regions and shallow trench regions, and connecting the n-type active regions, the p-type active regions, the deep trench regions and the shallow trench regions with resistors in a preset resistor matrix to form a 2D1R unit, wherein for each n-well region, one n-type active region is arranged every two p-type active regions at intervals and is used as an n+ leading-out terminal; All 2D1R cells are connected to a predetermined word line, bit line, and reset line to form a 2D1R array.
  6. 6. The method for producing 2D1R according to claim 5, The size of the 2D1R unit is 12F2.
  7. 7. The method of claim 5, wherein the 2D1R array is prepared by, The process of intercepting the corresponding n-type active region, p-type active region, deep trench region and shallow trench region and connecting with resistors in a preset resistor matrix to form a 2D1R unit comprises the following steps: Selecting a group of adjacent n-well regions and p-well regions; And connecting one p-type active region in the n-well region with one n-type active region in the p-well region in parallel and then connecting the p-type active region with the bottom of one resistor in a preset resistor matrix.
  8. 8. The method of claim 7, wherein the 2D1R array is prepared by, The process of connecting all 2D1R cells to the preset word lines, bit lines and reset lines to form a 2D1R array includes: for each of the 2D1R units, And connecting the selected n-well region with the corresponding word line through an n+ extraction terminal, and connecting the selected p-well region with the corresponding reset line through a p+ extraction terminal.
  9. 9. The method for producing 2D1R according to claim 8, For each n-well region, all n+ leading-out terminals are led out and connected in parallel to form corresponding word lines; for each p-well region, all the p+ leading-out terminals are led out and connected in parallel to form corresponding reset lines.

Description

2D1R array structure and preparation method thereof Technical Field The invention relates to the technical field of operation circuit design, in particular to a 2D1R array structure and a preparation method thereof. Background The array structure of the 2D1R (2-diode-1-resistor, two diodes and one resistor) can implement SET (write operation), RESET operation and READ (READ operation) on the bipolar resistive random access memory device. For the 2D1R array structure, the conventional 2D1R array structure is to connect two diodes back-to-back and then connect the two diodes in series with a resistor to form a control unit, and conventional implementation methods in industry include several methods, such as a patent scheme with a patent publication number CN110047867, in which a driving current needs to flow through a well resistor with a relatively high resistance value, so that a larger IR drop (voltage drop) is generated, so that when reaching a selected resistor far from a well lead-out end, the voltage drop is larger, which is unfavorable for performing a SET operation or a RESET operation. As another example, patent publication CN109427839 discloses a scheme in which all diodes are formed using the same type of well (both n-type well and p-type well), so that it is difficult to achieve complete isolation between wells by deep isolation trenches. Based on the above technical problems, there is a need for a 2D1R array of IR drop that has a good isolation effect from well to well and can effectively reduce well resistance. Disclosure of Invention In view of the above problems, the present invention is to provide a 2D1R array structure and a method for manufacturing the same, so as to solve the problems of poor isolation performance between wells and easy generation of larger IR drop in the existing 2D1R array structure. The invention provides a 2D1R array structure, which comprises m word lines, m reset lines and n bit lines, wherein the m word lines and the m reset lines are transversely arranged and are in one-to-one correspondence, the n bit lines are longitudinally arranged, wherein m and n are integers, m is more than or equal to 2, n is more than or equal to 2, and The memory unit comprises a first diode, a second diode and a resistor, wherein one end of the resistor is connected with the corresponding bit line, the other end of the resistor is respectively connected with the positive electrode of the first diode and the negative electrode of the second diode, the negative electrode of the first diode is connected with the corresponding word line, and the positive electrode of the second diode is connected with the corresponding reset line. It is furthermore preferred that, during reading, For the memory cells which are not selected in the 2D1R array structure, the bit line is at 0V voltage, the word line is at 0V voltage, and the reset line is at 0V voltage; wherein, the vrd is more than or equal to 0.3V and less than or equal to 1V. It is furthermore preferred that, during writing, For the memory cells selected in the 2D1R array structure, the bit line is at the Vset voltage, the word line is at the 0V voltage, and the reset line is at the 0V voltage; Wherein Vset is more than or equal to 2.0V and less than or equal to 3.5V. In addition, it is preferable that, during the reset process, For the memory cells selected in the 2D1R array structure, the bit line is at 0V voltage, the word line is at Vreset voltage, and the reset line is at Vreset voltage; for unselected memory cells in the 2D1R array structure, the bit line is set at Vreset voltage, the word line is set at Vreset voltage, and the reset line is set at 0V voltage; wherein, the vreset is less than or equal to 1.5V and less than or equal to 3.5V. In another aspect, the present invention further provides a method for preparing the 2D1R array as described above, where the method includes: Forming alternately arranged n-well regions and p-well regions by means of ion implantation; forming a deep trench region at the junction of the n-well region and the p-well region through an etching process, and arranging shallow trench regions in each n-well region and each p-well region through the etching process; Processing the deep trench region and the shallow trench region through filling and grinding processes so as to separate adjacent n-well regions from p-well regions through the deep trench region, and forming separated active regions in each n-well region and each p-well region through the shallow trench region; processing each active region by means of ion implantation to form an n-type active region and a p-type active region in each n-well region and each p-well region; Intercepting a corresponding n-type active region, a p-type active region, a deep trench region and a shallow trench region, and connecting the corresponding n-type active region, the p-type active region, the deep trench region and the shallow trench region with a resistor