Search

CN-115714126-B - Gate array structure integrated device and preparation method thereof

CN115714126BCN 115714126 BCN115714126 BCN 115714126BCN-115714126-B

Abstract

The application discloses an integrated device with a grid array structure and a preparation method thereof, relating to the technical field of semiconductor devices, comprising a substrate; the semiconductor device comprises a substrate, a buffer layer, a channel layer, a barrier layer, a passivation layer, a first groove, a second groove, a first grid, a second grid, a first grid and a second grid, wherein the buffer layer is positioned on one side of the substrate, the channel layer is positioned on one side of the buffer layer, which is away from the substrate, the barrier layer is positioned on one side of the channel layer, which is away from the substrate, the passivation layer is positioned on one side of the barrier layer, which is away from the substrate, the first groove penetrates through the passivation layer and the barrier layer along the direction perpendicular to the substrate, at least part of the channel layer, the second groove penetrates through the passivation layer and the barrier layer along the direction perpendicular to the substrate, the second groove is positioned between the first grooves, the first grid is used as a radio-frequency grid, the first grid comprises a first branch part and a second branch part, the first branch part is positioned in the first groove of the channel layer, the second branch part is positioned in the second groove, the first branch part and the second branch part forms an array structure, the second grid is a direct-current grid, and the second grid and the first grid is arranged at intervals along the second direction. The application can effectively ensure the high linearity of the integrated device signal.

Inventors

  • ZHANG MENG
  • ZOU XU
  • MA XIAOHUA
  • YANG LING
  • HOU BIN
  • WU MEI
  • HAO YUE

Assignees

  • 西安电子科技大学

Dates

Publication Date
20260505
Application Date
20221008

Claims (7)

  1. 1. A gate array structure integrated device, characterized by a gallium nitride-based high electron mobility field effect transistor, comprising: A substrate; a buffer layer located at one side of the substrate; The channel layer is positioned on one side of the buffer layer, which is away from the substrate; a barrier layer positioned on one side of the channel layer away from the substrate; a passivation layer positioned on one side of the barrier layer away from the substrate; a first trench penetrating the passivation layer and the barrier layer in a direction perpendicular to the substrate, and at least a portion of the channel layer; The second groove penetrates through the passivation layer and the barrier layer along the direction perpendicular to the substrate, is positioned between the first grooves and is communicated with the first grooves; The first grid is positioned at one side of the buffer layer, which is away from the substrate, and is a radio frequency grid, the first grid comprises a first branch part and a second branch part, the first branch part is positioned in the first groove of the channel layer, the second branch part is positioned in the second groove, and the first branch part and the second branch part form an array structure; The second grid is located on one side, away from the substrate, of the barrier layer, is a direct current grid, extends along a first direction, and is arranged with the first grid at intervals along a second direction, the second grid comprises a third branch part and a fourth branch part, the third branch part is located in a third groove, the fourth branch part covers the third branch part, the second grid is a direct current grid and is of a T-shaped or I-shaped structure, the structure of the second grid comprises a grid and a grid cap and plays a role of switching, and the first direction is intersected with the second direction.
  2. 2. The gate array structure integrated device of claim 1, wherein the first branch portions and the second branch portions are alternately arranged along a first direction.
  3. 3. The gate array structure integrated device according to claim 1, wherein an orthographic projection of the third branch portion on the substrate overlaps an orthographic projection of the fourth branch portion on the substrate in a direction perpendicular to the substrate.
  4. 4. The gate array structure integrated device of claim 1, wherein an orthographic projection of the third leg onto the substrate is located on an orthographic projection of the fourth leg onto the substrate in a direction perpendicular to the substrate.
  5. 5. The integrated gate array structure device of claim 1, wherein a depth of the first trench in the channel layer in a direction perpendicular to the substrate is less than 20nm.
  6. 6. The integrated device of claim 1, further comprising a source electrode and a drain electrode, wherein the source electrode and the drain electrode are spaced apart from each other on a side of the trench layer facing away from the substrate, and the first gate electrode and the second gate electrode are positioned between the source electrode and the drain electrode.
  7. 7. A method for manufacturing a gate array structure integrated device, characterized in that the method is applied to the gate array structure integrated device according to any one of claims 1 to 6, and the method comprises: Providing the substrate; sequentially manufacturing the buffer layer, the channel layer, the barrier layer and the passivation layer on the substrate; Etching grooves on the passivation layer and the barrier layer, and manufacturing a source electrode and a drain electrode; Etching the first groove and the second groove on the passivation layer, manufacturing the first branch part of the first grid electrode in the first groove, and manufacturing the second branch part of the first grid electrode in the second groove.

Description

Gate array structure integrated device and preparation method thereof Technical Field The invention belongs to the technical field of semiconductor devices, and particularly relates to an integrated device with a grid array structure and a preparation method thereof. Background The antenna is used as a component for receiving and transmitting electromagnetic wave signals and is a core accessory of some terminal equipment such as a mobile phone, wherein 5G is used as a new generation communication technology, and along with the increase of frequency bands, the innovation of a plurality of technologies and standards is brought, so that the design and the manufacture of the antenna are difficult, and the antenna is further developed towards the direction of high complexity and integration. In the prior art, with the improvement of the complexity of the radio frequency front-end switch circuit and the increase of the area, the isolation and the insertion loss are deteriorated to a certain extent, and meanwhile, the linearity of the radio frequency front-end device is also deteriorated due to the degradation of the carrier mobility of the device channel. Therefore, there is a need to solve the problems of the prior art that the number of devices at the power amplifier end is large, the area is large, the switching speed is slow, and the signal linearity is deteriorated. Disclosure of Invention In order to solve the problems in the prior art, the invention provides a grid array structure integrated device and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme: in a first aspect, the present application provides a gate array structure integrated device, comprising: A substrate; A buffer layer located at one side of the substrate; The channel layer is positioned on one side of the buffer layer, which is away from the substrate; a barrier layer positioned on a side of the channel layer facing away from the substrate; The passivation layer is positioned on one side of the barrier layer, which is away from the substrate; a first trench penetrating the passivation layer and the barrier layer in a direction perpendicular to the substrate, and at least a portion of the channel layer; the second groove penetrates through the passivation layer and the barrier layer along the direction perpendicular to the substrate, is positioned between the first grooves and is communicated with the first grooves; The first grid electrode is positioned at one side of the buffer layer, which is far away from the substrate, and is a radio frequency grid, and comprises a first branch part and a second branch part, wherein the first branch part is positioned in a first groove of the channel layer, the second branch part is positioned in a second groove, and the first branch part and the second branch part form an array structure; The second grid is positioned on one side of the barrier layer, which is away from the substrate, and is a direct current grid, the second grid extends along a first direction, the second grid and the first grid are arranged at intervals along a second direction, the second grid comprises a third branch part and a fourth branch part, the third branch part is positioned in a third groove, the fourth branch part covers the third branch part, and the first direction is intersected with the second direction. In a second aspect, the present application further provides a method for manufacturing an integrated device with a gate array structure, which is applied to the integrated device with a gate array structure provided by the present application, and the method includes: Providing a substrate; sequentially manufacturing a buffer layer, a channel layer, a barrier layer and a passivation layer on a substrate; etching grooves on the passivation layer and the barrier layer, and manufacturing a source electrode and a drain electrode; etching a first groove and a second groove on the passivation layer, manufacturing a first branch part of the first grid electrode in the first groove, and manufacturing a second branch part of the first grid electrode in the second groove. The invention has the beneficial effects that: According to the grid array structure integrated device and the manufacturing method thereof, on one hand, the first grid and the second grid are integrated on the same device, namely, the radio frequency switch and the Power Amplifier (PA) are integrated on the same device through the double-grid structure, the first grid is the radio frequency grid, the array structure is adopted to play a role in Power amplification, the second grid is the direct current grid, the T-shaped or I-shaped structure is adopted, the structure comprises the grid and the grid cap to play a role in switching, the radio frequency switch and the Power Amplifier are integrated on the same device, the number of radio frequency front-end devices can be reduced,