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CN-115732011-B - Serial interface with shadow registers and associated systems, apparatus, and methods

CN115732011BCN 115732011 BCN115732011 BCN 115732011BCN-115732011-B

Abstract

Serial interfaces with shadow registers, and associated systems, devices, and methods are described herein. In one embodiment, the serial interface is an IEEE 1500 interface such as an interface die of a high bandwidth memory HBM device. The IEEE 1500 interface includes (a) a main packed data register WDR configured to store first information received in a first packed serial input WSI signal, (b) a shadow WDR configured to store second information received in a second WSI signal, and (c) a multiplexer. The multiplexer is configured to (i) receive the first information from the primary WDR, (ii) receive the second information from the shadow WDR, and (iii) output the first information or the second information based at least in part on a control signal input into the multiplexer.

Inventors

  • K. G. verhahn
  • D.S. MILLER

Assignees

  • 美光科技公司

Dates

Publication Date
20260512
Application Date
20220719
Priority Date
20210901

Claims (20)

  1. 1. An IEEE 1500 interface, comprising: A main package data register WDR configured to store first information received in the first package serial input WSI signal; A shadow WDR configured to store second information received in the second WSI signal; a multiplexer configured to (a) receive the first information from the primary WDR, (b) receive the second information from the shadow WDR, and (c) output the first information or the second information based at least in part on a control signal input into the multiplexer, and A counter configured to output the control signal to the multiplexer based at least in part on a value stored by the counter.
  2. 2. The IEEE 1500 interface of claim 1, wherein: The counter is configured to receive an enable signal having a first state and a second state; Disabling the counter from updating the value stored by the counter when the enable signal is in the first state, and When the enable signal is in the second state, the counter is enabled to update the value stored by the counter.
  3. 3. The IEEE 1500 interface of claim 2, wherein, when the enable signal is in the first state, the multiplexer is configured to output the first information received from the master WDR.
  4. 4. The IEEE 1500 interface of claim 2, wherein: the counter is further configured to receive an update signal; the update signal includes an IEEE 1500 packaged serial port update UPDATEWR signal, and When the enable signal is in the second state, the counter is configured to update the value stored by the counter each time the UPDATEWR signal is asserted according to a transition of the IEEE 1500 packed serial portion clock WRCK signal.
  5. 5. The IEEE 1500 interface of claim 4, wherein: The value stored by the counter has a limit, and When the value reaches the limit, a next update of the value by the counter resets the value or causes the value to wrap around to an initial state corresponding to the state of the value when the enable signal was in the first state.
  6. 6. The IEEE 1500 interface of claim 1, wherein the shadow WDR is a duplicate WDR of the primary WDR such that the shadow WDR has the same register size as the primary WDR.
  7. 7. The IEEE 1500 interface of claim 1, wherein: the shadow WDR is configured to receive an enable signal; Disabling the shadow WDR from loading the second information contained in the second WSI signal when the enable signal is in a first state, and When the enable signal is in a second state, the shadow WDR is enabled to load the second information contained in the second WSI signal.
  8. 8. The IEEE 1500 interface of claim 1, wherein: The shadow WDR is a first shadow WDR; the IEEE 1500 interface further includes a second shadow WDR configured to store third information received in a third WSI signal, an The multiplexer is further configured to (i) receive the third information from the second shadow WDR, and (ii) output the first information, the second information, or the third information based at least in part on the control signal input into the multiplexer.
  9. 9. The IEEE 1500 interface of claim 8, wherein: The first shadow WDR is configured to receive a first enable signal that, when asserted, enables the first shadow WDR to load the second information received in the second WSI signal; The second shadow WDR is configured to receive a second enable signal that, when asserted, enables the second shadow WDR to load the third information received in the third WSI signal, an The first enable signal is different from the second enable signal.
  10. 10. The IEEE 1500 interface of claim 1, further comprising, in addition to said primary WDR and said shadow WDR, an encapsulated boundary register WBR and an encapsulated bypass register WBY.
  11. 11. A method of operating a serial interface, the method comprising: loading first information for a first register of the serial interface, wherein the first register has a first output in communication with a first input of a multiplexer of the serial interface; Loading second information for a second register of the serial interface, wherein the second register is a replica of the first register, and wherein the second register has a second output in communication with a second input of the multiplexer; Outputting the first information to a mode latch via an output of the multiplexer when a control signal input into the multiplexer is in a first state, and The second information is output to the mode latch via the output of the multiplexer when the control signal is in a second state different from the first state.
  12. 12. The method of claim 11, wherein loading the second register includes asserting an enable signal of the second register such that the second register is enabled to load the second information.
  13. 13. The method of claim 11, wherein loading the first register includes loading the first register with the first information in response to receiving an instruction to select an operating mode of a memory device that includes the serial interface.
  14. 14. The method of claim 11, further comprising updating a value of a counter such that the control signal transitions from the first state to the second state.
  15. 15. The method of claim 14, wherein updating the value of the counter includes (a) asserting an enable signal such that the counter is enabled to update the value, and (b) asserting an IEEE 1500 packed serial port update UPDATEWR signal in accordance with a transition of an IEEE 1500 packed serial port clock WRCK signal.
  16. 16. The method of claim 15, further comprising (a) de-asserting the enable signal such that the counter is disabled from updating the value, and (b) resetting the value in response to de-asserting the enable signal.
  17. 17. The method of claim 14, further comprising maintaining the control signal in the first state until (a) the counter is enabled and (b) the value of the counter is updated.
  18. 18. The method as recited in claim 11, further comprising: Loading a third register of the serial interface with third information, wherein the third register is another copy of the first register, wherein the third information is different from the first information or the second information, and wherein the third register has a third output in communication with a third input of the multiplexer, and The third information is output to the mode latch via the output of the multiplexer when the control signal is in a third state different from the first state and the second state.
  19. 19. The method according to claim 18, wherein: Loading the second information for the second register includes enabling the second register using a first enable signal, and Loading the third information for the third register includes enabling the third register using a second enable signal different from the first enable signal.
  20. 20. A high bandwidth memory HBM device comprising a memory device including one or more core dies, a mode latch, and an interface die having a serial interface, wherein the serial interface comprises: A main register configured to store first information received in the first input signal; a shadow register configured to store second information received in the second input signal; A multiplexer configured to (a) receive the first information from the main register, (b) receive the second information from the shadow register, and (c) output the first information or the second information to the mode latch based at least in part on a control signal input into the multiplexer, and A counter configured to output the control signal to the multiplexer based at least in part on a value stored by the counter.

Description

Serial interface with shadow registers and associated systems, apparatus, and methods Technical Field The present disclosure relates to serial interfaces having one or more shadow registers, and associated systems, apparatuses, and methods. For example, several embodiments of the present disclosure are directed to serial test interfaces for High Bandwidth Memory (HBM) devices that include at least one shadow register in addition to a main register for storing information (e.g., serial commands, address bits, and/or data sets). Background A semiconductor device (e.g., a processor, a memory device, a memory system, or a combination thereof) may include one or more semiconductor circuits configured to store and/or process information. For example, the semiconductor device may include a memory device, such as a volatile memory device, a non-volatile memory device, or a combination device. Memory devices such as Dynamic Random Access Memory (DRAM) and/or High Bandwidth Memory (HBM) may utilize electrical energy to store and access data. As technology advances in other areas and applications for semiconductor devices increase, the market has been looking for faster, more efficient, and smaller devices. To meet market demands, semiconductor devices are continuously improved. In general, improvements may include increasing circuit density, increasing operating speed or otherwise reducing operating latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Disclosure of Invention According to an aspect of the present application, an IEEE 1500 interface is provided. The IEEE 1500 interface includes a master encapsulated data register (WDR) configured to store first information received in a first encapsulated serial input (WSI) signal, a shadow WDR configured to store second information received in a second WSI signal, and a multiplexer configured to (a) receive the first information from the master WDR, (b) receive the second information from the shadow WDR, and (c) output the first information or the second information based at least in part on a control signal input into the multiplexer. According to another aspect of the application, a method is provided. The method includes loading a first register of a serial interface with first information, wherein the first register has a first output in communication with a first input of a multiplexer of the serial interface, loading a second register of the serial interface with second information, wherein the second register is a replica of the first register, and wherein the second register has a second output in communication with a second input of the multiplexer, outputting the first information to a mode latch via an output of the multiplexer when a control signal input into the multiplexer is in a first state, and outputting the second information to the mode latch via the output of the multiplexer when the control signal is in a second state different from the first state. According to yet another aspect of the present application, a High Bandwidth Memory (HBM) device is provided. The HBM device includes a memory device including one or more core dies, a mode latch, and an interface die having a serial interface, wherein the serial interface includes a main register configured to store first information received in a first input signal, a shadow register configured to store second information received in a second input signal, and a multiplexer configured to (a) receive the first information from the main register, (b) receive the second information from the shadow register, and (c) output the first information or the second information to the mode latch based at least in part on a control signal input into the multiplexer. Drawings The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only. 1A-1E are partial schematic block diagrams of example memory systems configured in accordance with various embodiments of the present technology. FIG. 2 is a partial schematic block diagram of a memory device configured in accordance with various embodiments of the technology. FIG. 3 is a partial schematic block diagram of a portion of a serial test interface configured in accordance with various embodiments of the present technique. FIG. 4 is a flowchart of a method of operating a portion of the serial test interface of FIG. 3 in accordance with various embodiments of the present technique. FIG. 5 is a schematic diagram of a system including a memory device in accordance with an embodiment of the present technology. Detailed Description As discussed in more detail below, the techniques disclosed herein relate to a serial interface having one o