CN-115732399-B - Semiconductor device and preparation method thereof

CN115732399BCN 115732399 BCN115732399 BCN 115732399BCN-115732399-B

Abstract

The invention discloses a semiconductor device and a preparation method thereof, wherein the method comprises the steps of providing an intermediate body, forming a blocking structure above an interlayer dielectric layer corresponding to a spacing area between adjacent gate stacks, etching the interlayer dielectric layer according to the blocking structure to form a contact opening exposing the gate stacks, removing the blocking structure, filling materials in the contact opening to form a contact unit, and further, the blocking structure is formed by etching a mask layer, the transverse dimension of the forming process can be flexibly adjusted, the opening dimension of an upper photoetching layer can be close to the width of an adjacent gate and a spacing area thereof in the direction, compared with the scheme in the prior art, the opening dimension of the photoetching layer can be enlarged, the photoetching difficulty is reduced, the contact opening can be accurately positioned above the gate stacks by virtue of the protection effect of the blocking structure, and the load area of the contact unit and the gate stacks is increased.

Inventors

LIN YINGZHI
ZHANG FENGYI
CAI SHANGYUAN
WANG RENLI

Assignees

广州集成电路技术研究院有限公司

Dates

Publication Date: 20260508
Application Date: 20210901

Claims (11)

1. A method of manufacturing a semiconductor device, the method comprising: Providing an intermediate, wherein the intermediate comprises a substrate, an interlayer dielectric layer and a patterned mask layer positioned on the interlayer dielectric layer, a source/drain structure and a plurality of grid stacks which are spaced from each other are formed above the substrate, and the interlayer dielectric layer is formed above the substrate and covers the source/drain structure and the grid stacks; Forming a blocking structure by etching the patterned mask layer above the interlayer dielectric layer corresponding to the spacing region between adjacent gate stacks; Depositing a patterned photoetching layer above the barrier structure and the interlayer dielectric layer, and etching the interlayer dielectric layer according to the photoetching layer to form a contact opening exposing the gate stack body and remove the barrier structure; and filling the contact openings with a material to form the contact units.
2. The method of claim 1, wherein the patterned masking layer exposes regions of the interlayer dielectric layer corresponding to pre-formed contact elements abutting the source/drain structures and overlies regions of the interlayer dielectric layer corresponding to pre-formed contact elements abutting the gate stack; the method comprises the steps of depositing a patterned photoetching layer above an interlayer dielectric layer and a patterned masking layer, etching the patterned masking layer according to the patterned photoetching layer to form a blocking structure above the interval region between adjacent gate stacks, and removing the rest of the photoetching layer.
3. The method of claim 2, wherein the sidewall of the blocking structure that coincides with the direction of extension of the gate stack is a non-curved plane.
4. The method of claim 2, wherein etching the patterned mask layer according to the patterned photoresist layer forms a barrier structure over the interlayer dielectric layer corresponding to the spacer region between adjacent gate stacks, specifically comprising: sequentially depositing a lower photoetching layer, a middle photoetching layer and an upper photoetching layer to form three photoetching layers, patterning the upper photoetching layer through exposure, and etching the middle photoetching layer according to the patterned upper photoetching layer to pattern the middle photoetching layer; adjusting the transverse dimension of the patterned intermediate photoetching layer through transverse etching; etching the lower lithography layer according to the size-adjusted patterned intermediate lithography layer to pattern the lower lithography layer; etching the patterned mask layer according to the patterned lower lithography layer to form a barrier structure; And removing the residual photoetching layer.
5. The method of claim 2, wherein etching the patterned mask layer in accordance with the patterned photoresist layer to form a blocking structure over the adjacent gate stack spacer region, comprises: Etching the patterned mask layer along the depth direction of the device according to the patterned photoresist layer to expose the interlayer dielectric layer; The remaining patterned mask layer is laterally etched to perform lateral sizing to form a barrier structure.
6. The method of claim 1, wherein the gate stack comprises a gate and a capping layer deposited over the gate, wherein the barrier structure comprises a first barrier layer abutting an interlayer dielectric layer; The first barrier layer and the covering layer are made of the same material, and/or the thickness of the first barrier layer is greater than or equal to 30nm, and/or the thickness difference between the first barrier layer and the covering layer is less than or equal to 5nm.
7. The method of claim 1, wherein the barrier structure comprises a first barrier layer abutting the interlayer dielectric layer and a second barrier layer disposed over the first barrier layer; The second barrier layer and the interlayer dielectric layer are made of the same material, and/or the thickness of the second barrier layer is greater than or equal to 5nm.
8. The method of claim 1 and any of claims 6-7, wherein the gate stack comprises a gate and a cap layer deposited over the gate, wherein the barrier structure comprises a first barrier layer abutting an interlayer dielectric layer and a second barrier layer disposed over the first barrier layer; depositing a patterned photoetching layer above the barrier structure and the interlayer dielectric layer, and etching the interlayer dielectric layer according to the photoetching layer to form a contact opening exposing the grid electrode stack body and remove the barrier structure, wherein the method comprises the steps of depositing the patterned photoetching layer above the barrier structure and the interlayer dielectric layer; Wherein the second barrier layer is removed while the interlayer dielectric layer is etched, and/or the first barrier layer is removed while the capping layer is removed by the etching.
9. The method of claim 1, wherein the barrier structure is a single layer structure, and the thickness of the barrier structure is greater than or equal to 45nm.
10. The method of claim 1 or 9, wherein the gate stack comprises a gate and a capping layer deposited over the gate; Depositing a patterned photoetching layer above the blocking structure and the interlayer dielectric layer, and etching the interlayer dielectric layer according to the photoetching layer to form a contact opening exposing the gate stack body and remove the blocking structure, wherein the method comprises the steps of depositing the patterned photoetching layer above the blocking structure and the interlayer dielectric layer; etching the interlayer dielectric layer according to the patterned photoetching layer to expose part of the covering layer, removing the residual photoetching layer, removing the blocking structure, and continuing etching to remove the covering layer to form a contact opening exposing the grid electrode.
11. A semiconductor device prepared by the method of any one of claims 1-10.

Description

Semiconductor device and preparation method thereof Technical Field The invention relates to the field of semiconductors, in particular to a semiconductor device and a preparation method thereof. Background In the prior art, the semiconductor processing window is continuously compressed along with the improvement of the integration level of the device, and even approaches to the design limit of optical equipment and etching equipment, which brings great challenges to the design of the device. For example, due to the shrinking process window, the forming space of the Contact unit (Contact) is greatly compressed, so that the originally separated Contact unit has a position deviation, and even the adjacent two Contact units have a communication condition, as shown in fig. 1, fig. 1 is a comparison diagram of an ideal situation and a semiconductor device actually produced, and fig. 1 is a top view. The essential cause of the aforementioned defects is in fact the process of forming the contact elements connecting the gate stacks. Referring to fig. 2, the semiconductor device of fig. 2 shows a cross-sectional structure of the AA position of fig. 1 a. In forming the contact elements connecting the gate stacks, a patterned photoresist layer 8' is typically deposited over the intermediate interlayer dielectric layer 6' thereof, and the interlayer dielectric layer is etched in accordance with the patterned photoresist layer to form contact openings 200' exposing the gate stacks. Ideally, the deposited patterned photoresist layer has adjacent gate stacks with the corresponding desired photoresist openings discontinuous from each other, as shown in fig. 1 a. However, in the actual production process, as the process node of the device is gradually reduced, the corresponding size of the lithography opening is also reduced, and the connection between the adjacent lithography openings is easy to appear, as shown in fig. 1 b. Thus, in an ideal state, the contact units above the adjacent gate stacks are not shifted in position and are not communicated with each other. However, as the integration level of the device increases, the critical dimension of the contact unit is approaching the lithography limit, so that the space for patterning in the lithography process is greatly compressed, the exposure is limited, and the dimension of the patterned lithography layer deviates, so that bridging occurs on the contact unit formed according to the lithography pattern. Disclosure of Invention The invention aims to solve the technical problem that the contact units in the prior art have position deviation and even the adjacent two contact units have communication, and provides a semiconductor device and a preparation method thereof. The technical scheme adopted by the invention for solving the technical problems is that a preparation method of a semiconductor device is constructed, and the method comprises the following steps: providing an intermediate body, wherein the intermediate body comprises a substrate and an interlayer dielectric layer, a source/drain structure and a plurality of grid stacks which are spaced from each other are formed above the substrate, and the interlayer dielectric layer is formed above the substrate and covers the source/drain structure and the grid stacks; forming a blocking structure above an interlayer dielectric layer corresponding to a spacing region between adjacent gate stacks; forming a contact opening exposing the gate stack on the interlayer dielectric layer and removing the blocking structure; and filling the contact openings with a material to form the contact units. Preferably, the intermediate further comprises a patterned mask layer on the interlayer dielectric layer, the patterned mask layer exposing a region of the interlayer dielectric layer corresponding to the contact unit preformed to abut the source/drain structure and covering a region of the interlayer dielectric layer corresponding to the contact unit preformed to abut the gate; The method comprises the steps of depositing a patterned mask layer on the interlayer dielectric layer and the patterned mask layer, etching the patterned mask layer according to the patterned mask layer to form a blocking structure on the interlayer dielectric layer corresponding to the interval region between the adjacent gate stacks, and removing the rest of the mask layer. Preferably, the side wall of the blocking structure, which is consistent with the extending direction of the gate stack, is a non-curved plane. Preferably, the forming a blocking structure above the interlayer dielectric layer corresponding to the interval region between the adjacent gate stacks specifically includes: sequentially depositing a lower photoetching layer, a middle photoetching layer and an upper photoetching layer to form three photoetching layers, patterning the upper photoetching layer through exposure, and etching the middle photoetching layer according to the pattern