CN-115758907-B - Ship target detection tracking power consumption optimization method based on heterogeneous SOC (system on chip) and electronic equipment

CN115758907BCN 115758907 BCN115758907 BCN 115758907BCN-115758907-B

Abstract

The invention relates to a heterogeneous SOC-based ship target detection tracking power consumption optimization method and electronic equipment, wherein the method comprises the following steps of constructing a plurality of algorithm model matrixes with different power consumption by adjusting bit precision and a neural network level; the method comprises the steps of collecting working states of all software by using a low-power CPU, calculating power consumption change of the software, controlling the FPGA for target detection and the high-performance CPU to be started and stopped according to the power consumption change, selecting a proper algorithm from an algorithm matrix and temporarily controlling the high-performance CPU for target tracking to be stopped in operation according to total power consumption and a preset power consumption threshold. According to the invention, on the basis of ensuring that ship target detection is completed efficiently, the balance between system power consumption and computing capacity is ensured by dynamically closing and opening the CPU and the FPGA and dynamically adjusting the detection algorithm, so that the power consumption is greatly reduced.

Inventors

WU XUEYOU
WANG CHAO
GAO JI
ZHANG RUI
SU HAO

Assignees

中国空间技术研究院

Dates

Publication Date: 20260508
Application Date: 20221128

Claims (5)

1. The ship target detection tracking power consumption optimization method based on the heterogeneous SOC is characterized by comprising the following steps of: s1, constructing a plurality of algorithm model matrixes with different power consumption by adjusting bit precision and a neural network level; s2, collecting working states of all the software by using a low-power-consumption CPU, and calculating power consumption changes of the software; s3, controlling the starting and the closing of the FPGA for target detection and the starting and the closing of the high-performance CPU for target tracking according to the power consumption change; S4, selecting an algorithm model and temporarily controlling the closing of a high-performance CPU (Central processing Unit) for target tracking in operation according to the total power consumption and a preset power consumption threshold; In the step S4, an algorithm model is selected according to the total power consumption and a preset power consumption threshold, and the algorithm model specifically includes: Step S401, calculating the total power consumption of the system in real time; Step S402, calculating the sum of the total power consumption of the system and the power consumption of a plurality of algorithm models, and confirming the optimal algorithm model according to the sum of the power consumption and a preset power consumption threshold; step S403, transmitting the algorithm model confirmed in the step S402 to an FPGA for target detection; in the step S402, it includes: comparing the power consumption with a preset power consumption threshold value in turn according to the relation of the power consumption and the power consumption from large to small, and confirming that the power consumption and the corresponding algorithm model are the optimal algorithm model when the power consumption and the power consumption are smaller than the preset power consumption threshold value; And when the minimum power consumption sum is larger than a preset power consumption threshold value, temporarily controlling the high-performance CPU to be turned off in operation until the target detection is completed, and then performing target tracking processing.
2. The method according to claim 1, characterized in that in said step S1, it comprises in particular: s11, performing fixed-point conversion on a convolution kernel on a convolution neural network; Step S12, adjusting bit precision; Step S13, adjusting the neural network level; s14, training a model on a high-performance GPU server; S15, generating an IP core, downloading the IP core and the model to the FPGA for testing, and calculating power consumption; and S16, repeatedly executing the steps S12 to S15, and constructing a plurality of algorithm model matrixes with different power consumption.
3. The method according to claim 1, characterized in that in said step S3, it comprises in particular: Step S301, judging whether the power consumption of the software is continuously smaller than or equal to a preset threshold value within a period of time; Step S302, when the power consumption of the target detection software is smaller than or equal to a preset threshold value, the target detection software can be determined to be in a standby state, and the FPGA is controlled to be closed; In step S303, when the power consumption of the target tracking software is less than or equal to the preset threshold, it may be determined that the target tracking calculation is not performed, and then the high-performance CPU is controlled to be turned off.
4. An electronic device comprising at least one low-performance CPU, at least one high-performance CPU, at least one FPGA, one or more memories, and one or more computer programs, wherein a processor is coupled to the memories, the one or more computer programs being stored in the memories, the processor executing the one or more computer programs stored in the memories when the electronic device is in operation, to cause the electronic device to perform the heterogeneous SOC-based ship target detection tracking power consumption optimization method of any of claims 1-3.
5. A computer readable storage medium for storing computer instructions which, when executed by a processor, implement the heterogeneous SOC-based vessel target detection tracking power consumption optimization method of any of claims 1 to 3.

Description

Ship target detection tracking power consumption optimization method based on heterogeneous SOC (system on chip) and electronic equipment Technical Field The invention relates to the technical field of ship target detection, in particular to a ship target detection tracking power consumption optimization method based on heterogeneous SOC and electronic equipment. Background With the continuous evolution of the battle concept and the battle system, only the battle situation is comprehensively and rapidly mastered, and decisions can be rapidly made to form battle advantages. The satellite has the characteristics of all weather, far sight and accurate sight, and can finish the detection and tracking of the ship targets through an image recognition technology. However, a large amount of time is consumed before the detection of the object detection software reaching the ground due to the large satellite image data volume, low satellite transmission efficiency and many circulation nodes. Therefore, in order to solve the timeliness problem of target detection, real-time detection and tracking on a satellite can be considered, and in view of the limitation of power consumption of the satellite, the detection equipment is required to have the characteristics of high efficiency, high reliability and low power consumption, and the traditional mode of a CPU and a GPU cannot meet the requirement. In recent years, image detection, identification and tracking technologies are widely researched and applied, but under the condition of low power consumption, the equipment detection accuracy and continuous tracking capability are still insufficient, and the problems of power consumption expansion and detection time extension are caused by the improvement of the detection capability. Disclosure of Invention In view of the technical problems, the invention provides a heterogeneous SOC-based ship target detection tracking power consumption optimization method and electronic equipment, which have the advantages of high reliability, high efficiency and low power consumption. The technical scheme for realizing the purpose of the invention is that the target detection tracking power consumption optimizing method based on the heterogeneous SOC ship comprises the following steps: s1, constructing a plurality of algorithm model matrixes with different power consumption by adjusting bit precision and a neural network level; s2, collecting working states of all the software by using a low-power-consumption CPU, and calculating power consumption changes of the software; s3, controlling the starting and the closing of the FPGA for target detection and the starting and the closing of the high-performance CPU for target tracking according to the power consumption change; and S4, selecting an algorithm model and temporarily controlling the closing of the high-performance CPU used for target tracking in operation according to the total power consumption and a preset power consumption threshold. According to an aspect of the present invention, in the step S1, specifically includes: s11, performing fixed-point conversion on a convolution kernel on a convolution neural network; Step S12, adjusting bit precision; Step S13, adjusting the neural network level; s14, training a model on a high-performance GPU server; S15, generating an IP core, downloading the IP core and the model to the FPGA for testing, and calculating power consumption; and S16, repeatedly executing the steps S12 to S15, and constructing a plurality of algorithm model matrixes with different power consumption. According to an aspect of the present invention, in the step S3, specifically includes: Step S301, judging whether the power consumption of the software is continuously smaller than or equal to a preset threshold value within a period of time; step S302, when the power consumption of the target detection software is smaller than or equal to a preset threshold value, determining that the target detection software is in a standby state, and controlling the FPGA to be closed; And step S303, when the power consumption of the target tracking software is smaller than or equal to a preset threshold value, determining that the target tracking software is in a standby state, and controlling the high-performance CPU to be turned off. According to one aspect of the present invention, in the step S4, an algorithm model is selected according to the total power consumption and a preset power consumption threshold, and specifically includes: Step S401, calculating the total power consumption of the system in real time; Step S402, calculating the sum of the total power consumption of the system and the power consumption of a plurality of algorithm models, and confirming the optimal algorithm model according to the sum of the power consumption and a preset power consumption threshold; and step S403, transmitting the algorithm model confirmed in the step S402 to the FPGA for target detection.