CN-115758957-B - Compiling method for realizing FPGAEDA software dynamic reconfigurable function

CN115758957BCN 115758957 BCN115758957 BCN 115758957BCN-115758957-B

Abstract

The invention provides a compiling method for realizing the FPGA EDA software dynamic reconfigurable function, which realizes the FPGA reconfigurable function from software compiling, and generates code streams respectively by separately designing, integrating, laying out and wiring a reconfigurable module and a full-function module, so that the dynamic reconfigurable is independent when designing, and the dynamic area function is independent when loading the code streams of a new replacement module, and the function of a dynamic area is independent because the code streams are independently separated when designing, and the function of a bus interface is realized by connecting a CLB, so that no special bus macro is needed to determine that the wiring channels among the modules are not changed, and correct connection is ensured.

Inventors

LI YUJIE
LIU YANG
YANG PEIYU

Assignees

中科亿海微电子科技（苏州）有限公司

Dates

Publication Date: 20260512
Application Date: 20221229

Claims (7)

1. A compiling method for realizing the dynamic reconfigurable function of FPGA EDA software is characterized by comprising the following steps when a full-function module designs an FPGA with the dynamic reconfigurable function: The method comprises the steps of 1, marking a reconfigurable module, meanwhile, designating a physical area of the reconfigurable module in a chip, namely a dynamic area, and recording the reconfigurable module and corresponding position information thereof in a user constraint file, wherein other areas are static areas; step 2, when the combination is carried out, logic on the reconfigurable module and the non-reconfigurable module is not combined and optimized; Step 3, marking the logic unit of the reconfigurable module as a reconfigurable logic unit when the generated netlist file is preprocessed; Step 4, during packaging, a reconfigurable logic unit and a logic unit without a mark are packaged separately, a logic cluster CLB packaged by the reconfigurable logic unit is marked as a reconfigurable CLB, a signal generated by the reconfigurable logic unit is marked as a reconfigurable signal, a signal passing through a dynamic area and a static area is split into two sections, the static area is divided into one section, the dynamic area is divided into one section and marked as a reconfigurable signal, the logic unit with the reconfigurable mark configured as an IO function is packaged into a connection CLB according to the scale of the logic cluster CLB, the connection CLB is used as a bus interface for connecting the dynamic area and the static area, the logic unit configured as an IO function is set as a direct connection function; And 5, respectively generating code streams of the full-function module and the reconfigurable module after the static area and the dynamic area are respectively laid out and wired.
2. The compiling method of claim 1, wherein the method for splitting the signal passing through the dynamic-static region into two segments is as follows: The method comprises the steps of finding out a start point and an end point end of a signal, dividing the signal into two sections from a passing point passing through a dynamic-static area, setting a virtual start point_virtual and a virtual end point end_virtual on the two separated sections, connecting the start point with the virtual end point end_virtual, connecting the virtual start point_virtual with the end point end, marking the section of signal connected with the virtual end point end_virtual by the start point if the start point is in a dynamic reconfigurable area, marking the section of signal connected with the virtual end point end_virtual by the start point as a reconfigurable signal, and marking the section of signal connected with the virtual end point end by the virtual start point_virtual if the end point end is in the dynamic reconfigurable area.
3. The compiling method according to claim 1, wherein step 2 further comprises checking that the reconfigurable module matches with the resources of the delimited physical area after synthesis, and if the physical resources for realizing the logical functions of the module contained in the delimited physical area cannot meet the resources required for realizing the functions of the reconfigurable module, giving a notification of insufficient resources in the physical area, and reassigning the physical area.
4. The compiling method according to claim 3, wherein the layout range of the reconfigurable CLB is constrained to be within a physical constraint area corresponding to the dynamic area when laying out, the signal set is traversed when laying out, the signal layout search range is constrained to be the dynamic area if the signal has a reconfigurable mark, and the signal layout search range is the static area if the signal has no reconfigurable mark.
5. The compiling method according to claim 4, wherein the number and type of IO designed in the top layer of the netlist cannot exceed the number and type of IO of the reconfigurable module in the full-function module when the replacing module is designed and compiled, and the replacing module is a user design module for replacing functions of the reconfigurable module.
6. The method of claim 5, wherein the replacement module, when compiling, packages the IO of the netlist, needs to match the connection properties of the connection CLBs at the time of full-function design, and the type of the signal needs to be consistent with the full-function module.
7. The compiling method according to claim 6, wherein the module layout wiring is replaced by restricting a layout wiring range to a corresponding physical restriction area.

Description

Compiling method for realizing FPGAEDA software dynamic reconfigurable function Technical Field The invention belongs to the field of integrated circuits, and particularly relates to a compiling method for realizing a dynamic reconfigurable function of FPGA EDA software. Background The FPGA EDA software is used for converting the system functions written in the hardware description language into downloading files through compiling modules such as synthesis, layout, wiring, code stream generation and the like, and downloading the downloading files into the FPGA to realize the system functions. If the functions of other circuits need to be realized, the source program needs to be modified, the compiling flow is re-executed, and the compiling flow is downloaded into the FPGA again to realize the preset functions. With the progress of technology, the scale of the FPGA is larger and the functions of a digital logic system are more and more complex, the FPGA chip is developing towards the ultra-large scale and high density, the achievable logic function and user design are more and more complex, and the compiling time of EDA software of the FPGA is longer and longer each time. The dynamic reconfiguration is to dynamically change the structure of the circuit in the working state of the FPGA system. This is accomplished primarily by reconfiguring or locally reconfiguring programmable logic devices in the system, with the reconfiguration or locally reconfiguring the code stream content depending on the implementation of EDA software technology. By defining specific regions, these regions can be reconfigured while other parts of the device are still running. The dynamic reconfiguration reduces the reconfiguration range and the number of units, greatly shortens the reconfiguration time, and completes the function conversion under the conditions that the system is not restarted and the equipment is not powered off. Therefore, the functions can be reduced, the board utilization rate can be improved, and the compiling and downloading speeds can be increased. The conventional EDA dynamic reconfiguration technique is based on partial dynamic reconfiguration of the modules, and its implementation requires a special bus macro to determine that the wiring channels between the modules are unchanged, ensuring proper connections. Disclosure of Invention The invention provides a compiling method and a device for realizing the FPGA EDA software dynamic reconfigurable function, which aims to solve the technical problem of directly loading a new function code stream of a reconfiguration region under the condition that a wiring channel between modules is not changed on the basis of not using a special bus macro. In order to solve the technical problems, the invention adopts the following technical scheme: a compiling method for realizing FPGA EDA software dynamic reconfigurable function, when designing FPGA with dynamic reconfigurable function in full function module, includes the following steps: The method comprises the steps of 1, marking a reconfigurable module, meanwhile, designating a physical area of the reconfigurable module in a chip, namely a dynamic area, and recording the reconfigurable module and corresponding position information thereof in a user constraint file, wherein other areas are static areas; step 2, when the combination is carried out, logic on the reconfigurable module and the non-reconfigurable module is not combined and optimized; Step 3, marking the logic unit of the reconfigurable module as a reconfigurable logic unit when the generated netlist file is preprocessed; Step 4, during packaging, the reconfigurable logic unit and the logic unit without the mark are packaged separately, a logic cluster CLB packaged by the reconfigurable logic unit is marked as a reconfigurable CLB, a signal generated by the reconfigurable logic unit is marked as a reconfigurable signal, a signal passing through a dynamic area and a static area is split into two sections, the static area is divided into one section, and the dynamic area is divided into one section and marked as a reconfigurable signal; And 5, respectively generating code streams of the full-function module and the reconfigurable module after the static area and the dynamic area are respectively laid out and wired. Further, the method for splitting the signal passing through the dynamic-static region into two sections is as follows: The method comprises the steps of finding out a start point and an end point end of a signal, dividing the signal into two sections from a passing point passing through a dynamic-static area, setting a virtual start point_virtual and a virtual end point end_virtual on the two separated sections, connecting the start point with the virtual end point end_virtual, connecting the virtual start point_virtual with the end point end, marking the section of signal connected with the virtual end point end_virtual by the start point if the star