CN-115758988-B - Method for compensating channel pair internal offset by differential via

Abstract

The invention discloses a method for compensating channel intra-pair offset of differential via holes, which comprises the steps of calculating offset time between differential signals, establishing a PCB and a differential via hole model by using obtained material parameters, simulating the established high-precision differential model, obtaining S parameters of a differential via hole structure through simulation, obtaining the actually-measured S parameters of the design and an internal offset skew value of the differential pair to calibrate a scale factor for 3D modeling, optimizing stub length difference h in the differential via hole structure, comparing whether an optimization result meets a design-allowed internal offset target value of the differential pair, if so, completing optimization, and if not, continuing to optimize stub length difference h. The invention has the advantages that the occupation of layout wiring space is small, the differential line can timely compensate the offset of the differential phase by the proposed differential via structure, and the influence on internal offset is effectively avoided.

Inventors

• CHEN YI
• ZHAO XIANG
• WU BOWEN
• YUAN ZHENYU
• WEI GUOJUN
• MAO LIMING

Assignees

• 无锡市同步电子科技有限公司

Dates

Publication Date

20260512

Application Date

20221130

Claims (2)

1. 1. A method for compensating for channel intra-pair offset by differential vias, comprising the steps of: Obtaining a PCB design requiring uncompensated differential offset, screening whether a link has a differential via, and if so, continuing the following steps; Calculating offset time between the differential signals NP; establishing a model of the PCB and the differential via hole by using the acquired material parameters; simulating the established high-precision differential model, and obtaining S parameters of the differential via structure through simulation, wherein the S parameters comprise insertion loss, return loss and offset skew value in the differential pair; Obtaining the actually measured S parameter and the offset skew value in the differential pair to calibrate the scaling factor for 3D modeling ; Simulating and optimizing stub length difference h in the differential via structure on a 3D model meeting the precision, so that offset skew of the differential structure is minimum, and a preset design target is met; Comparing whether the optimization result meets the design allowable differential pair internal offset target value, if so, completing optimization, and if not, continuing to optimize stub length difference h; and fitting the differential via hole compensation pair internal offset delay, wherein the fitting formula is as follows: wherein Td is differential via compensation in-pair offset delay, f is the frequency of the transmitted signal, sigma is the adjustment scale factor, The relative dielectric constant of the PCB substrate is h, the length difference of the stub between the differential vias is h, D is the aperture of the via, D 1 is the diameter of the via bonding pad, and D 2 is the diameter of the via isolation; the parameters f, sigma, And h, D and D 1 、D 2 establish a high-precision 3D structure simulation model in the HFSS 3D module, and obtain the adjusted scaling factor sigma after fitting optimization through actual measurement.
2. 2. The method of compensating for channel intra-pair offset of differential vias according to claim 1, wherein if the link does not have differential vias, then the intra-pair is compensated in a wire-wrap manner.

Description

Method for compensating channel pair internal offset by differential via Technical Field The invention belongs to the technical field of printed circuit boards, and particularly relates to a method for compensating channel pair internal offset by a differential via. Background With the continuous progress and increasing demand of modern information processing technology and the increasing popularity of technologies such as big data, cloud computing and internet of things, the demand for ultra-high speed and large broadband communication products is becoming stronger. The wide application of differential lines in the field of PCB design, the rational optimization of differential signal integrity, has become a key to the success of today's system design. The differential signal is that the driving end sends two equivalent and opposite signals, and the receiving end judges whether the logic state is 0 or 1 by comparing the difference value of the two voltages. And the pair of PCB routing carrying the differential signals is referred to as differential routing. Wherein differential intra-pair shifting is one of the important loops affecting differential signal quality. The logic device offset (skew) is defined by the JEDEC standard as the "time difference between two events that should occur simultaneously". The offset (intra-pairskew) in the differential pair is the difference in delay between the positive and negative terminals of the differential pair. The differential signals reach the terminals at different times after being transmitted through differential lines on the PCB, resulting in a delay difference, thereby affecting signal quality. The reduction of the size of the PCB board card and the chip packaging leads to the rapid reduction of the PCB wiring space due to the improvement of the system complexity, and higher requirements are put on the compensation mode of the internal offset of the differential pair. The existing differential pair internal offset design method occupies a design space no matter large bulges and small bulges, and is easy to introduce abrupt changes of impedance and difficult to ensure the signal quality. There are many reasons for the offset in the differential pair, such as right angle routing, BGA pin design limitations, driver rise and fall time mismatch, glass fiber effects, etc. In particular, BGA pin designs are inevitable in limiting the routing of PCB differential signal lines. The quantization unit of the offset in the differential pair of the PCB is time, the time is combined with the propagation speed of the signal on the PCB channel in design, the length to be compensated is obtained, and the length deviation in the pair is compensated by using the winding. In the prior art, the method of compensating the channel pair internal offset by the differential via hole needs to compensate the short signal line by a winding mode. The Chinese patent publication No. CN 113420527B, which is a method, device, system and storage medium for calculating the equal length around the differential line, provides a calculation method for automatically determining the number of arcs required to be generated so as to obtain the number of bulges to be compensated and compensating in the design on the basis of the technology of calculating the offset length error pair inner equal length of the differential line NP based on design software. Chinese patent CN 108630650A discloses a method and a device for BGA fan-out phase compensation, wherein the method comprises the steps of fan-out differential signals in a BGA area to form fan-out through holes of the differential signals, and carrying out wire winding compensation on differential signal wires by adopting a preset mode at the fan-out through holes of the differential signals. The two patents require a layout space to perform the winding compensation, and the winding forms are various, but are determined for the shape or position. The need to occupy layout wiring space cannot be avoided, new impedance discontinuities can be introduced by the windings, and due to the need for additional co-layer space, nearby compensation cannot often be achieved, resulting in increased differential phase mismatch lengths. Disclosure of Invention In view of this, the present invention combines existing design and production processes to propose a method for minimizing the internal offset of a differential pair of a PCB, and optimizes the PCB design by using the method to seek to minimize the internal offset of the differential pair, thereby improving the integrity of the differential signal. The invention discloses a method for compensating channel intra-pair offset by a differential via, which comprises the following steps: Obtaining a PCB design requiring uncompensated differential offset, screening whether a link has a differential via, and if so, continuing the following steps; Calculating offset time between the differential signals NP; establishing