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CN-115760672-B - Test model building method, test method and detection equipment

CN115760672BCN 115760672 BCN115760672 BCN 115760672BCN-115760672-B

Abstract

The embodiment of the application relates to the field of semiconductor testing, in particular to a method for establishing a test model, a test method and detection equipment, which comprise the steps of providing a semiconductor structure, wherein N chip structures are stacked in the semiconductor structure, and the chip structure comprises a semiconductor layer and M metal layers stacked on the semiconductor layer; the method comprises the steps of selecting a metal layer or a semiconductor layer from M metal layers as a preset test layer of a chip structure, acquiring interval time of each chip structure based on the preset test layer, wherein the acquisition of the interval time of the chip structure comprises the steps of applying an excitation signal to the preset test layer, generating an indication signal by the preset test layer based on the excitation signal, detecting the indication signal at the top of the semiconductor structure, acquiring interval time from the application of the excitation signal to the detection of the indication signal, establishing a first sub-test image of the chip structure by taking frequency of the excitation signal as a first coordinate and the interval time as a second coordinate, and integrating the first sub-test image of each chip structure in the test image.

Inventors

  • XU KAI

Assignees

  • 长鑫存储技术有限公司

Dates

Publication Date
20260512
Application Date
20210902

Claims (13)

  1. 1. The method for establishing the test model is characterized by comprising the following steps of: Providing a semiconductor structure, wherein N chip structures are stacked in the semiconductor structure, the chip structures comprise a semiconductor layer and M metal layers stacked on the semiconductor layer, and N and M are natural numbers greater than or equal to 2; Selecting one metal layer from the M metal layers or selecting the semiconductor layer as a preset test layer of the chip structure, wherein the selection mode of the preset test layer of each chip structure is the same, and acquiring the interval time of each chip structure based on the preset test layer; the acquiring the interval time of the chip structure comprises: Applying an excitation signal to the preset test layer, wherein the preset test layer generates an indication signal based on the excitation signal, the indication signal is detected at the top of the semiconductor structure, and the interval time from the application of the excitation signal to the detection of the indication signal is acquired; Establishing a first sub-test image of the chip structure by taking the frequency of the excitation signal as a first coordinate and the interval time as a second coordinate, and integrating the first sub-test image of each layer of the chip structure into a test image; acquiring a first test image and a second test image; The first test image is acquired for the semiconductor layer based on the preset test layer; the second test image is obtained for M metal layers, which are positioned at the top of the metal layers, based on the preset test layer; acquiring the test image based on the first test image, the second test image and weights corresponding to the first test image and the second test image; acquiring a time difference value of the first reference time and the second reference time; The first reference time is the interval time when the preset test layer is the semiconductor layer; the second reference time is the interval time when the preset test layer is the metal layer positioned at the top of the M metal layers; acquiring a first layer number, wherein the first layer number is the layer number of the metal layer between the preset test layer and the semiconductor layer; obtaining a second layer number, wherein the second layer number is the layer number of the metal layer between the preset test layer and the metal layer positioned at the top of the M metal layers; Acquiring an upward floating range of the test image based on the time difference value and the ratio of the first layer number to the sum of the first layer number and the second layer number; And acquiring the floating range of the test image based on the time difference value and the ratio of the second layer number to the sum of the first layer number and the second layer number.
  2. 2. The method for building a test model according to claim 1, wherein the obtaining the interval time of the chip structure further comprises: changing the frequency of the excitation signal to obtain L frequency adjustment signals, wherein L is a natural number greater than or equal to 2; and acquiring the interval time of each layer of the chip structure under different frequencies based on the adjustment signal of each frequency.
  3. 3. The method for building a test model according to claim 1, wherein the predetermined test layer is the semiconductor layer.
  4. 4. The method for building a test model according to claim 1, wherein the predetermined test layer is M metal layers, the metal layer being located on top of the metal layer.
  5. 5. The method of claim 1, wherein the indication signal comprises a thermal signal generated by the predetermined test layer based on the stimulus signal or an optical signal generated by the predetermined test layer based on the stimulus signal.
  6. 6. A test method for acquiring an abnormal position of a semiconductor structure to be tested, comprising: Acquiring a test image of a standard semiconductor structure based on the method for establishing a test model according to any one of claims 1 to 5; acquiring the provided semiconductor structure to be tested, and acquiring a detection image of the semiconductor structure to be tested, wherein the detection image is a test image corresponding to the semiconductor structure to be tested, which is acquired based on the method for establishing the test model according to any one of claims 1-5; Drawing the detection image into the test image, judging whether the semiconductor structure to be detected is abnormal or not, and judging the chip structure where the abnormal position is located; And taking out the chip structure with the abnormal position and positioning the abnormal position in the chip structure.
  7. 7. The test method according to claim 6, wherein the preset test layer set to acquire the test image is the same as the preset test layer set to acquire the detection image.
  8. 8. The test method according to claim 7, comprising: The preset test layer is a semiconductor layer; The method for judging the chip structure of the abnormal position by drawing the detection image into the test image comprises the steps of obtaining a first sub-test image which is smaller than the detection image in interval time and is nearest to the detection image in the test image, and taking the chip structure represented by the first sub-test image as the position of the abnormal position.
  9. 9. The test method according to claim 7, comprising: The preset test layer is the metal layer positioned at the top of the M metal layers; the method for judging the chip structure of the abnormal position by drawing the detection image into the test image comprises the steps of obtaining a first sub-test image which is larger than the detection image in interval time and is nearest to the detection image in the test image, and taking the chip structure represented by the first sub-test image as the position of the abnormal position.
  10. 10. The test method according to claim 7, comprising: the preset test layer is any one of M metal layers; acquiring an upward floating range and a downward floating range of the test image; The method includes drawing the detection image into the test image, and judging a chip structure where the abnormal position is located, wherein the method includes judging a section where the detection image belongs based on the test image, the floating range and the floating range, acquiring a first sub-test image represented by a corresponding section based on the section where the detection image belongs, and taking the chip structure represented by the first sub-test image as the position where the abnormal position is located.
  11. 11. The method according to any one of claims 6 to 10, wherein the frequency of the excitation signal used to acquire the test image is the same as the frequency of the excitation signal used to acquire the test image.
  12. 12. A detection apparatus, characterized by comprising: a storage module for storing test images obtained by the method for building a test model according to any one of claims 1 to 5; the excitation module is used for providing an excitation signal for the semiconductor structure to be tested; The first detection module is used for acquiring an indication signal at the top of the semiconductor structure to be detected; the processing module is connected with the excitation module and the first detection module and is used for acquiring the interval time from the application of the excitation signal to the acquisition of the indication signal; the analysis module is connected with the storage module and the processing module and is used for judging whether the semiconductor structure to be tested is abnormal or not based on the test image and the interval time and analyzing a chip structure of the semiconductor structure to be tested, wherein the abnormal position of the chip structure is located; the acquisition module is connected with the analysis module and is used for acquiring a chip structure where the abnormal position is located in the semiconductor structure to be detected; the second detection module is connected with the acquisition module and used for positioning the abnormal position in the chip structure.
  13. 13. The detection apparatus according to claim 12, wherein the excitation module comprises: the excitation unit is used for providing an excitation signal for the semiconductor structure to be tested; And the control unit is connected with the excitation unit and is used for adjusting the frequency of the excitation signal provided by the excitation unit.

Description

Test model building method, test method and detection equipment Technical Field The present application relates to the field of semiconductor testing, and in particular, to a method for building a test model, a test method, and a test apparatus. Background With the development of advanced 3D packaging processes (such as Stack process, TSV process, etc.), the number of chips stacked on the same substrate is increasing, and the capacity of memory chips is also increasing and the speed is also increasing. In addition, as the size of semiconductor process is continuously reduced, the probability of chip failure caused by defects generated in the device and manufacturing process is increased, and meanwhile, the difficulty in positioning defects in the semiconductor device is also increased due to the increase of the number of chips stacked on the substrate. Therefore, there is a need for a simple, feasible and cost effective method of defect localization for locating defects in semiconductor devices. Disclosure of Invention The embodiment of the application provides a test model building method, a test method and detection equipment, and provides a defect analysis method which is simple, feasible, efficient and convenient for 3D stacked semiconductor chips. The embodiment of the application provides a method for establishing a test model, which comprises the steps of providing a semiconductor structure, stacking N chip structures in the semiconductor structure, wherein the chip structures comprise semiconductor layers and M metal layers stacked on the semiconductor layers, N and M are natural numbers greater than or equal to 2, selecting one metal layer or the semiconductor layer from the M metal layers as a preset test layer of the chip structure, wherein the selection mode of the preset test layer of each chip structure is the same, acquiring the interval time of each chip structure based on the preset test layer, and acquiring the interval time of the chip structure comprises the steps of applying an excitation signal to the preset test layer, generating an indication signal based on the excitation signal by the preset test layer, detecting the indication signal at the top of the semiconductor structure, acquiring the interval time from the application of the excitation signal to the detection of the indication signal, establishing a first sub-test image of the chip structure by taking the frequency of the excitation signal as a first coordinate and the interval time as a second coordinate, and integrating the first sub-test image of each chip structure into the test image. The interval time of each chip in the semiconductor structure is obtained by selecting a preset test layer, sub-test images corresponding to the chip structure are obtained based on the interval time, the sub-test images corresponding to the chips are integrated in one test image, namely, the interval time required by each chip in the semiconductor structure to generate an indication signal under normal conditions is reflected through the test image, and the position of the defective chip in the semiconductor structure can be rapidly judged when the test image is used for judging later. In addition, the method for obtaining the interval time of the chip structure further comprises the steps of changing the frequency of the excitation signal, obtaining L frequency adjusting signals, wherein L is a natural number greater than or equal to 2, and obtaining the interval time of each layer of chip structure under different frequencies based on the adjusting signals of each frequency. The frequency of the excitation signal is changed to obtain a test image under more frequencies, so that the accuracy of the established test model is improved. In addition, the preset test layer is a semiconductor layer. The semiconductor layer is a bottom layer structure of the chip structure, and the time for transmitting the indication signal to the top of the semiconductor structure is longest, so that the subsequent failure positioning by using the established test model is facilitated. In addition, the preset test layer is a metal layer positioned at the top of the M metal layers. The top metal layer is the top layer structure of the chip structure, the time for transmitting the indication signal to the top of the semiconductor structure is shortest, and the subsequent failure positioning by using the established test model is facilitated. In addition, a first test image and a second test image are acquired, the first test image is acquired for the semiconductor layer based on a preset test layer, the second test image is acquired for a metal layer positioned on the top of the M metal layers based on the preset test layer, and the test images are acquired based on the first test image, the second test image and weights corresponding to the first test image and the second test image. The accuracy of the built test model is further ensured by weighting the firs