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CN-115760865-B - Layout distributed processing method and storage medium

CN115760865BCN 115760865 BCN115760865 BCN 115760865BCN-115760865-B

Abstract

The invention discloses a distributed processing method and a storage medium of a layout. The distributed processing method of the layout comprises the steps of dividing the layout into a plurality of blocks, coloring and setting priorities, processing the blocks according to the order of the priorities from high to low, distributing different blocks with the same priority into different DP tasks for parallel processing, obtaining processing time of each block, searching the combinable blocks according to the order of the priorities from high to low, wherein the condition that the combinable blocks meet is that the sum of the processing time of two adjacent blocks and the block with the interval lower than the current priority among the blocks is smaller than or equal to the maximum processing time of the block with the current priority, merging the three blocks into one block with the current priority, and performing the next round of loop iteration until the preset ending condition is reached after all the priority searches are completed. The invention can dynamically color and reduce the idle waiting time of CPU in the operation process.

Inventors

  • Du Yaojuan
  • LI YAO
  • CHEN HONG
  • BAI GENG

Assignees

  • 深圳国微福芯技术有限公司

Dates

Publication Date
20260505
Application Date
20221123

Claims (5)

  1. 1. A distributed processing method of a layout is characterized by comprising the following steps: step 1, dividing a layout into a plurality of blocks; Step 2, coloring all the blocks so that the color of the blocks around each block is different from that of the block; Step 3, defining different priorities based on different colors of the blocks; Step 4, processing the blocks according to the sequence from high to low of the priority, and distributing different blocks with the same priority to different DP tasks for parallel processing; step 5, obtaining the processing time required by each block; And 6, searching the combinable blocks according to the order of the priorities from high to low, wherein the combinable blocks meet the condition that two adjacent blocks with the same color exist in the blocks with the current priority, the adjacent blocks are separated by one block with different priorities, the priority of the block between the two adjacent blocks with the same color is lower than the current priority, the sum of the processing time of the two adjacent blocks and the block between the two adjacent blocks is smaller than or equal to the maximum processing time of the block with the current priority, the priorities of the two adjacent blocks and the block spaced between the two adjacent blocks are combined into one block with the current priority, and after all priority searching is finished, the step 4 is returned until the preset ending condition is reached.
  2. 2. A distributed processing method of a layout according to claim 1, wherein the size of the tiles is in the range of 15-50 microns.
  3. 3. A distributed processing method according to claim 1, wherein the priority of the blocks is defined to change from high to low according to the order of the values of the colors from low to high.
  4. 4. The method for distributed processing of a layout according to claim 1, wherein the preset end condition is that a preset number of loops is reached or a convergence target of the layout is reached.
  5. 5. A computer readable storage medium storing a computer program, wherein the computer program when run performs a distributed processing method of a layout according to any of claims 1 to 4.

Description

Layout distributed processing method and storage medium Technical Field The invention relates to the field of semiconductor manufacturing, in particular to a distributed processing method of a layout. Background In order to transfer the pattern from the reticle to the surface of the silicon wafer, an exposure step, a development step performed after the exposure step, and an etching step after the development step are generally required. In the exposure step, light irradiates the silicon wafer coated with photoresist through a light-transmitting area in the mask, the photoresist is subjected to chemical reaction under the irradiation of the light, in the development step, a photoetching pattern is formed by utilizing the difference of the dissolution degree of the photosensitive photoresist and the non-photosensitive photoresist to the developer, the transfer of the pattern from the mask to the photoresist is realized, and in the etching step, the silicon wafer is etched based on the photoetching pattern formed by the photoresist layer, and the pattern of the mask is further transferred to the silicon wafer. In semiconductor manufacturing, as the design size is continuously reduced, the design size is more and more close to the limit of a photoetching imaging system, the diffraction effect of light becomes more and more obvious, optical image degradation is finally generated on a design pattern, the actually formed photoetching pattern is severely distorted relative to the pattern on a mask plate, and finally the actual pattern formed by photoetching on a silicon wafer is different from the design pattern, and the phenomenon is called optical proximity effect (OPE: optical Proximity Effect). In order to correct the optical proximity effect, an optical proximity correction (OPC: optical Proximity Correction) is generated. The core idea of the optical proximity correction is to build an optical proximity correction model based on the consideration of canceling the optical proximity effect, and design a photomask pattern according to the optical proximity correction model, so that although the optical proximity effect occurs in the lithographic pattern corresponding to the photomask pattern, since the cancellation of the phenomenon has been considered when designing the photomask pattern according to the optical proximity correction model, the lithographic pattern after lithography is close to the target pattern that the user actually wants. Currently the dominant technology node (65 nm and below manufacturing process) employs model-based OPC corrections. The OPC correction is first optically modeled on the reticle using the Hopkins equation (Hopkin's equation) and results in an in-air light intensity distribution (AERIAL IMAGE). And then the light intensity distribution in the air is converted into photoacid distribution (RESIST IMAGE) in the photoresist by a photoresist compact model (compact model). The photoacid is washed away by the developer, so that a simulated pattern (connours) of the layout can be directly obtained from RESIST IMAGE. The size of the whole layout can reach the centimeter level sometimes, and the consumed computing resources far exceed that of a single CPU, so that the whole layout needs to be processed by using distributed computation. Specifically, the whole layout is divided into blocks (tiles), and all tiles are colored into four colors. And sequentially processing tiles according to the priority levels to complete one loop iteration. This conventional distributed processing method has a problem of inefficiency. Assuming that color-0 has a higher priority than color-1, all color-0 blocks are processed in parallel when color-0 blocks are processed, and color-1 blocks must be processed after all color-1 blocks are completed. It is most desirable if all color-0 tiles can be completed at approximately the same time. However, in practical operation, it may happen that some of color-0 blocks require CPU time, and most of other blocks require time. Since color-1 partitioning can only be processed after all color-0 partitioning is completed, a large number of CPUs are left in an idle state, resulting in a large amount of wasted computing resources. Disclosure of Invention In order to solve the technical problem of CPU resource waste in the prior art when the layout is subjected to OPC correction processing, the invention provides a distributed processing method and a storage medium of the layout. The distributed processing method of the layout provided by the invention comprises the following steps: step 1, dividing a layout into a plurality of blocks; step2, coloring all the blocks; Step 3, defining different priorities based on different colors of the blocks; Step 4, processing the blocks according to the sequence from high to low of the priority, and distributing different blocks with the same priority to different DP tasks for parallel processing; step 5, obtaining the processing time