CN-115763540-B - Semiconductor structure and forming method thereof

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the method comprises the steps of forming a first auxiliary gate structure in a first leading-out region, forming a source doping region in an active region and on a body region around each main gate structure, forming a first groove in the first auxiliary gate structure after the source doping region is formed, forming a second groove in the source doping region and the body region between adjacent main gate structures and extending along a second direction, implanting first doping ions into an epitaxial layer below the first groove and the second groove to form a first implantation region at the bottom of the body region between adjacent main gate structures and at the bottom of the first auxiliary gate structure, forming a first conductive plug and a first conductive layer located on the first conductive plug in the first groove after the first implantation region is formed, and forming a second conductive plug and a second conductive layer located on the second conductive plug in the second groove, thereby improving the performance of the device and being beneficial to saving the manufacturing cost.

Inventors

• XU ZHAOZHAO
• QIAN WENSHENG

Assignees

• 华虹半导体(无锡)有限公司
• 上海华虹宏力半导体制造有限公司

Dates

Publication Date

20260505

Application Date

20221122

Claims (20)

1. 1. A semiconductor structure, comprising: The epitaxial device comprises a substrate and an epitaxial layer positioned on the substrate, wherein the epitaxial layer comprises an active region and a peripheral region surrounding the active region, the peripheral region comprises two first extraction regions, the two first extraction regions are respectively positioned at two sides of the active region, and the first extraction regions and the active region are distributed along a first direction; A body region within the epitaxial layer; A plurality of main gate structures located within the active region, the plurality of main gate structures penetrating the body region in a direction perpendicular to the substrate surface, the plurality of main gate structures being parallel to the first direction and arranged along a second direction, the first direction and the second direction being perpendicular to each other; A first auxiliary gate structure located within the first extraction region, the first auxiliary gate structure penetrating the body region in a direction perpendicular to the substrate surface, the first auxiliary gate structure being parallel to the second direction and electrically interconnected with the main gate structure; A first conductive plug within the first auxiliary gate structure, the first conductive plug extending along the second direction; A source doped region located on the body region within the active region, the source doped region being located around the main gate structure; A second conductive plug located between adjacent ones of the main gate structures, the second conductive plug being located within the source doped region and the body region, the second conductive plug extending along the first direction; a first conductive layer on the epitaxial layer, the first conductive layer including a first lead-out parallel to the second direction, the first lead-out and the first auxiliary gate structure being electrically connected by the first conductive plug; the second conductive layer is positioned on the epitaxial layer and is electrically connected with the source doping region and the body region through the second conductive plugs; and the first injection region is positioned in the epitaxial layer, and is positioned at the bottom of the body region and the bottom of the first auxiliary gate structure between the adjacent main gate structures.
2. 2. The semiconductor structure of claim 1, wherein said peripheral region further comprises a second extraction region parallel to said first direction and on one side of said active region and said first extraction region, said first conductive layer further comprising an end portion on said second extraction region, said end portion being parallel to said first direction and electrically interconnected with said first extraction portion.
3. 3. The semiconductor structure of claim 2, wherein the peripheral region further comprises a plurality of shielding regions arranged from outside to inside, each shielding region comprising a first shielding region and a second shielding region surrounding the first shielding region, the semiconductor structure further comprising a first shielding structure located at the first shielding region, the first shielding structure comprising a second implanted region and a third conductive plug located on the second implanted region, the second implanted region being located at the bottom of the body region, a second shielding structure located at the second shielding region, the second shielding structure comprising a dummy gate structure extending through the body region in a direction perpendicular to the substrate surface.
4. 4. The semiconductor structure of claim 3, wherein said first shield region comprises first and second regions separated from each other, said first and second regions being aligned along said first direction, said third conductive plug being located within said first and second regions, said end portion being electrically interconnected with said third conductive plug within said first region, said first region further having a second auxiliary gate structure comprising a second auxiliary gate dielectric layer and a second auxiliary gate located on said second auxiliary gate dielectric layer, said third conductive plug further being located within said second auxiliary gate structure, and a portion of said second implant region being located at a bottom of said second auxiliary gate structure.
5. 5. The semiconductor structure of claim 2, wherein said active region further has a charge balance region therein, wherein said source doped region and said main gate structure are located within said active region outside of said charge balance region, wherein said first conductive layer further comprises a second lead-out on said charge balance region, said second lead-out being electrically interconnected with said end portion.
6. 6. The semiconductor structure of claim 5, further comprising a charge balance structure within said charge balance region, said charge balance structure comprising a third implanted region at a bottom of said body region and a fourth conductive plug within said body region, said charge balance structure comprising a plurality of third regions parallel to said first direction and two fourth regions on either side of said plurality of third regions, said two fourth regions and said plurality of third regions being arranged in said first direction and being connected to one end of said plurality of third regions, respectively, said fourth conductive plug being electrically interconnected with said second lead-out portion and said fourth conductive plug being isolated from said second conductive plug.
7. 7. The semiconductor structure of claim 6, wherein the charge balance structure further comprises a third auxiliary gate structure, the fourth conductive plug is located in the third auxiliary gate structure, the third injection region is located at the bottom of the third auxiliary gate structure, the third auxiliary gate structure isolates the third injection region from the body region and is electrically interconnected with the main gate structure, and the third auxiliary gate structure comprises a third gate dielectric layer and a third auxiliary gate located on the third gate dielectric layer.
8. 8. The semiconductor structure of claim 1, further comprising an interlayer dielectric layer on said epitaxial layer, said first conductive plug, said second conductive layer, said second conductive plug further being within said interlayer dielectric layer.
9. 9. The semiconductor structure of claim 1, wherein the substrate and the source doped region are of a first conductivity type, the body region and the first implanted region are of a second conductivity type, the first conductivity type and the second conductivity type being different.
10. 10. The semiconductor structure of claim 1, wherein the main gate structure comprises a main gate dielectric layer and a main gate electrode on the main gate dielectric layer, and wherein the first auxiliary gate structure comprises a first auxiliary gate dielectric layer and a first auxiliary gate electrode on the first auxiliary gate dielectric layer.
11. 11. A method of forming a semiconductor structure, comprising: Providing a substrate; forming an epitaxial layer on the substrate, wherein the epitaxial layer comprises an active region and a peripheral region surrounding the active region, the peripheral region comprises two first extraction regions, the two first extraction regions are respectively positioned at two sides of the active region, and the first extraction regions and the active region are arranged along a first direction; Forming a body region within the epitaxial layer; Forming a plurality of main gate structures in the active region, wherein the main gate structures penetrate through the body region in the direction perpendicular to the surface of the substrate, the main gate structures are parallel to the first direction and are distributed along the second direction, and the first direction and the second direction are perpendicular to each other; Forming a first auxiliary gate structure in the first leading-out region, wherein the first auxiliary gate structure penetrates through the body region in a direction perpendicular to the surface of the substrate, is parallel to the second direction and is electrically interconnected with the main gate structure; Forming a source doped region within the active region and on the body region around each main gate structure; Forming a first groove in the first auxiliary gate structure after the source doping region is formed, wherein the first groove extends along the second direction, and a second groove is formed in the source doping region and the body region between adjacent main gate structures, and the second groove extends along the first direction; Implanting first doping ions into the epitaxial layer under the first groove and the second groove to form a first implantation region at the bottom of the body region between adjacent main gate structures and the bottom of the first auxiliary gate structure; after the first injection region is formed, a first conductive plug and a first conductive layer on the first conductive plug are formed in the first groove, and a second conductive plug and a second conductive layer on the second conductive plug are formed in the second groove.
12. 12. The method of forming a semiconductor structure of claim 11 wherein said peripheral region further comprises a second extraction region parallel to said first direction and on one side of said active region and said first extraction region, wherein said first conductive layer on said first extraction region is a first extraction portion and further comprises an end portion on said second extraction region parallel to said first direction and electrically interconnected with said first extraction portion.
13. 13. The method of forming a semiconductor structure as recited in claim 12 wherein said peripheral region further comprises a plurality of shield regions disposed from outside to inside, each of said shield regions comprising a first shield region and a second shield region surrounding said first shield region, said method comprising forming a shield structure within each of said shield regions, said shield structure comprising a first shield structure within said first shield region and a second shield structure within said second shield region.
14. 14. The method of forming a semiconductor structure of claim 13, wherein said first shield region comprises a first region and a second region separated from each other, said first region and said second region being arranged along said first direction, said end portion being electrically interconnected with said first shield structure in said first region, said method of forming a first shield structure comprising forming a third recess in said body region of said first region and said second region after forming said source doped region, implanting second dopant ions into said epitaxial layer under said third recess, forming a second implanted region at the bottom of said body region, forming a third conductive plug in said third recess after forming said second implanted region, and taking said third conductive plug and said second implanted region as said first shield structure.
15. 15. The method of forming a semiconductor structure of claim 14, wherein said first shielding structure further comprises forming a second auxiliary gate structure in said first region after forming said body region and before forming said source doped region, said second auxiliary gate structure extending through said body region in a direction perpendicular to said substrate surface, said second auxiliary gate structure comprising a second auxiliary gate dielectric layer and a second auxiliary gate on said second auxiliary gate dielectric layer, said third recess further being located in said second auxiliary gate structure, said second implanted region further being located at a bottom of said second auxiliary gate structure.
16. 16. The method of forming a semiconductor structure of claim 13, wherein said second shielding structure forming comprises forming said second shielding structure within said second shielding region after forming said body region and before forming a source doped region, said second shielding structure comprising a dummy gate structure extending through said body region in a direction perpendicular to said substrate surface.
17. 17. The method of forming a semiconductor structure of claim 12, wherein said active region further has a charge balance region therein, said charge balance region being adjacent to said second extraction region, wherein said source doped region and said main gate structure are located within said active region outside of said charge balance region, wherein said first conductive layer further comprises a second extraction region located on said charge balance region, said second extraction region being electrically interconnected with said end portion.
18. 18. The method of claim 17, further comprising forming a charge balance structure in the charge balance region after the forming of the body region and before the forming of the first conductive layer, the charge balance structure including a third injection region at a bottom of the body region and a fourth conductive plug in the body region, the charge balance structure including a third region parallel to the first direction and two fourth regions on both sides of the third regions, the two fourth regions and the third regions being arranged in the first direction and being connected to one end of the third regions, the fourth conductive plug being electrically interconnected with the second extraction portion and the fourth conductive plug being isolated from the second conductive plug, respectively.
19. 19. The method of forming a semiconductor structure of claim 18, wherein said charge balance structure further comprises a third auxiliary gate structure, said fourth conductive plug is located in said third auxiliary gate structure, said third implant region is located at a bottom of said third auxiliary gate structure, said third auxiliary gate structure isolates said third implant region from said body region and is electrically interconnected with said main gate structure, said third auxiliary gate structure comprises a third gate dielectric layer and a third auxiliary gate electrode located on said third gate dielectric layer.
20. 20. The method of forming a semiconductor structure of claim 19, wherein said method of forming a charge balance structure comprises forming a third auxiliary gate structure in said third region and said fourth region after forming said body region and before forming said source doped region, said third auxiliary gate structure extending through said body region in a direction perpendicular to said substrate surface and electrically interconnecting said main gate structure, forming a fourth recess in said third auxiliary gate structure after forming said source doped region, implanting third dopant ions into said fourth recess to form said third implanted region, forming said fourth conductive plug in said fourth recess, said second extraction portion of said first conductive layer being located on said fourth conductive plug.

Description

Semiconductor structure and forming method thereof Technical Field The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same. Background With the growing demand for electronic consumer products, the demand for power MOSFETs (Metal Oxide Semiconductor Field-Effect Transistor) is increasing, such as in disk drives, automotive electronics, and power devices. The trench gate MOSFET (Trench MOSFET) has a low on-resistance, a low gate-drain charge density, and a large current capacity due to a high integration level of the device, so that the trench gate MOSFET (Trench MOSFET) has low switching loss and high switching speed, and is widely applied to the field of low-voltage power. A trench gate MOSFET is a device having a vertical conduction channel in which current flows vertically from the drain terminal to the source terminal. The on-resistance (Rsp) and Breakdown Voltage (BV) of the trench gate MOSFET are one of important parameter indexes, and the product competitiveness can be improved by obtaining higher breakdown voltage and lower on-resistance. In order to improve the on-resistance of medium-high voltage (50 v-200 v) trench gate MOSFETs, super junction-trench gate MOSFET concepts are proposed. Taking an N-channel trench gate as an example, the bottom end of a P-type ion implantation region (P-pilar) for the depletion of the auxiliary drift region would be as close as possible to the highly doped substrate to make the depletable N-type drift region long. In order to improve the characteristics of the super junction-trench gate MOSFET device, the bottom end of the P-type ion implantation region is as close to the highly doped substrate as possible, so that the concentration of the whole epitaxial layer can be increased. However, the P-type ion implantation region implantation increases the manufacturing cost of the process, so that the advantage of the super junction-trench gate MOSFET is reduced. Therefore, the existing trench gate MOSFET device formation process needs to be further improved. Disclosure of Invention The invention solves the technical problem of providing a semiconductor structure and a forming method thereof so as to reduce the manufacturing cost of a trench gate MOSFET device. In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure, which comprises a substrate and an epitaxial layer positioned on the substrate, wherein the epitaxial layer comprises an active region and a peripheral region surrounding the active region, the peripheral region comprises two first extraction regions, the two first extraction regions are respectively positioned at two sides of the active region, and the first extraction regions and the active region are arranged along a first direction; a body region within the epitaxial layer; a plurality of main gate structures located within the active region, the plurality of main gate structures extending through the body region in a direction perpendicular to the substrate surface, the plurality of main gate structures being parallel to the first direction and arranged in a second direction, the first direction and the second direction being perpendicular to each other, a first auxiliary gate structure located within the first extraction region, the first auxiliary gate structure extending through the body region in a direction perpendicular to the substrate surface, the first auxiliary gate structure being parallel to the second direction and electrically interconnected with the main gate structure, a first conductive plug located within the first auxiliary gate structure, the first conductive plug extending in the second direction, a source doped region located on the body region within the active region, the source doped region being located around the main gate structure, a second conductive plug located between adjacent main gate structures and within the source doped region and the body region, the second conductive plug being located within the first extraction layer extending in the first direction, the first conductive plug being located on the first extension layer, the first extraction part is electrically connected with the first auxiliary grid structure through the first conductive plug, the second conductive layer is arranged on the epitaxial layer and is electrically connected with the source doping region and the body region through the second conductive plugs, and the first injection region is arranged in the epitaxial layer and is positioned at the bottom of the body region and the bottom of the first auxiliary grid structure between adjacent main grid structures. Optionally, the peripheral region further comprises a second extraction region parallel to the first direction and located on one side of the active region and the first extraction region, and the first conductive layer further compri