CN-115774136-B - Detection circuit and detection method

Abstract

A detection method is used for detecting a memory chip. The detection method comprises the steps of coupling a detection circuit to a first area and a second area of a memory chip, wherein the second area and the first area are not overlapped with each other, inputting a first detection signal from the detection circuit to the first area of the memory chip, burning out a memory cell of the detection circuit, and inputting a second detection signal from the detection circuit to the second area of the memory chip. The invention provides a detection circuit and a detection method, which are used for saving the detection time and cost for detecting a memory chip and preventing the memory chip from being damaged in detection.

Inventors

• LIN YANDE
• Rao Ruixiu

Assignees

• 南亚科技股份有限公司

Dates

Publication Date

20260508

Application Date

20211231

Priority Date

20210907

Claims (10)

1. 1. A method for inspecting a memory chip, comprising: Coupling a detection circuit to a first region and a second region of the memory chip, wherein the second region and the first region do not overlap each other; inputting a first detection signal from the detection circuit to the first region of the memory chip; burn the memory cell of the detection circuit, and A second detection signal is input from the detection circuit to the second region of the memory chip.
2. 2. The method of claim 1, wherein the step of inputting the first detection signal from the detection circuit to the first region of the memory chip comprises: judging whether the first area of the memory chip is normal or not; Wherein the step of inputting the second detection signal from the detection circuit to the second region of the memory chip comprises: judging whether the second area of the memory chip is normal or not.
3. 3. The method of detecting according to claim 1, further comprising: the switch of the detection circuit is conducted to serve as a resistor so as to transmit the second detection signal to the second area of the memory chip according to the control signal.
4. 4. The method of detecting according to claim 1, further comprising: The detection circuit is removed from the memory chip during fabrication.
5. 5. The method of claim 1, wherein the memory chip further comprises a plurality of word lines and a plurality of bit lines, and wherein the step of inputting the first detection signal from the detection circuit to the first region of the memory chip comprises: A plurality of detection signals are respectively input to the word lines or the bit lines.
6. 6. The method of claim 5, wherein the step of inputting the first detection signal from the detection circuit to the first region of the memory chip comprises: And inputting the detection signals to the word lines and the bit lines simultaneously.
7. 7. A sensing circuit for sensing a memory chip, the sensing circuit comprising: an input board coupled to the first region of the memory chip for inputting a first detection signal to the first region of the memory chip, and And the memory cell is coupled to the input board and the second area of the memory chip, wherein the second area and the first area are not overlapped with each other, and the memory cell is burnt out so that a second detection signal input from the input board is transmitted to the second area of the memory chip.
8. 8. The detection circuit of claim 7, further comprising: and a switch, wherein the switch is turned on to act as a resistor for transmitting the second detection signal to the second region of the memory chip according to a control signal.
9. 9. The sensing circuit of claim 8, wherein the memory chip comprises a two-dimensional array of memory and a three-dimensional array of memory, wherein the memory chip comprises a plurality of word lines and a plurality of bit lines, wherein the word lines are perpendicular to the bit lines, wherein the word lines and the bit lines form a grid matrix on the memory chip, wherein the grid matrix comprises a first portion and a second portion, wherein the second portion surrounds the first portion, wherein the second portion does not overlap the first portion, wherein the sensing circuit comprises a first sensing circuit and a second sensing circuit, wherein the first sensing circuit is coupled to the word lines, wherein the second sensing circuit is coupled to the bit lines.
10. 10. The detection circuit of claim 7, further comprising: the detection boards are used for returning a plurality of detection results of the first detection signal and the second detection signal to the input board.

Description

Detection circuit and detection method Technical Field The invention relates to a detection circuit and a detection method. In detail, the present invention relates to a detection circuit and a detection method for detecting a memory chip. Background In the prior art, focused Ion Beam (FIB) circuit repair techniques have been used in memory chips to understand leakage current of a plurality of word lines or a plurality of bit lines. Focused Ion Beam (FIB) circuit repair techniques often employ a Focused Ion Beam to modify the logic or circuit connectivity of a circuit chip or memory chip. Due to the Focused Ion Beam (FIB) circuit repair technique, a plurality of word lines or a plurality of bit lines from the edge to the center of the memory chip are often burned out for electrical analysis. However, the use of a focused ion beam can result in damage to the circuit chip or memory chip. Therefore, the skilled person cannot know where the leakage current is generated by the circuit chip or the memory chip. Therefore, the above technology has many drawbacks, and those skilled in the art will be required to develop other suitable detection methods. Disclosure of Invention One aspect of the present invention relates to a detection method. The detection method is used for detecting the memory chip. The detection method comprises the steps of coupling a detection circuit to a first area and a second area of a memory chip, wherein the second area and the first area are not overlapped with each other, inputting a first detection signal from the detection circuit to the first area of the memory chip, burning out a memory cell of the detection circuit, and inputting a second detection signal from the detection circuit to the second area of the memory chip. In some embodiments, the step of inputting the first detection signal from the detection circuit to the first region of the memory chip includes determining whether the first region of the memory chip is normal, and the step of inputting the second detection signal from the detection circuit to the second region of the memory chip includes determining whether the second region of the memory chip is normal. In some embodiments, the sensing method further includes turning on a switch of the sensing circuit as a resistor to transmit a second sensing signal to a second region of the memory chip according to the control signal. In some embodiments, the method of detecting further includes removing the detection circuit from the memory chip during the manufacturing process. In some embodiments, the memory chip also includes a plurality of word lines and a plurality of bit lines. The step of inputting a first detection signal from the detection circuit to the first region of the memory chip includes inputting a plurality of detection signals to a plurality of word lines or a plurality of bit lines, respectively. In some embodiments, the step of inputting the first detection signal from the detection circuit to the first region of the memory chip includes inputting a plurality of detection signals to a plurality of word lines and a plurality of bit lines simultaneously. Another aspect of the invention relates to a detection circuit. The detection circuit is used for detecting the memory chip. The detection circuit includes an input board and a memory cell. The input board is coupled to the first area of the memory chip. The input board is used for inputting a first detection signal to a first area of the memory chip. The memory cell is coupled to the input board and the second region of the memory chip. The second region and the first region do not overlap each other. The memory cell is burned out so that the input board inputs a second detection signal to a second area of the memory chip. In some embodiments, the detection circuit further comprises a switch. The switch is turned on to act as a resistor to transmit a second detection signal to a second region of the memory chip according to the control signal. In some embodiments, the memory chip includes a two-dimensional array memory and a three-dimensional memory. The memory chip includes a plurality of word lines and a plurality of bit lines. The plurality of word lines are perpendicular to the plurality of bit lines. A plurality of word lines and a plurality of bit lines form a grid matrix on the memory chip. The grid matrix includes a first portion and a second portion. The second portion surrounds the first portion. The second portion and the first portion do not overlap each other. The detection circuit comprises a first detection circuit and a second detection circuit. The first detection circuit is coupled to the plurality of word lines. The second detection circuit is coupled to the plurality of bit lines. In some embodiments, the detection circuit further comprises a plurality of detection boards. The plurality of detection boards are used for returning a plurality of detection results of the first detection sig