CN-115776762-B - Hybrid integrated low-noise power circuit

Abstract

The invention relates to a hybrid integrated low-noise power circuit which comprises a stratum GND copper-clad middle layer, a high-frequency alternating current node L1-2 with an inductor L1 at the blank of the stratum GND copper-clad middle layer, wherein an input Vin node L1-1 is arranged in the top layer and is connected with the input end of the inductor L1, the other end of the inductor is connected with the SW end of a controller N1 and is communicated with the node L1-2, a diode V1 is arranged in the bottom layer, the P electrode of the diode V1 is communicated with the node L1-2, the output end of the diode V1 is connected with a capacitor C3, the other end of the C3 is connected with a GND copper-clad layer, and the GND copper-clad layer is connected with the GND of an N1 controller and is simultaneously connected with the input GND end. The invention has the advantages that Vin is input into three layers of loops through which current flows through the inductor L1, the area of the loops through which the current flows is almost zero, the high-frequency magnetic flux variation is greatly reduced, noise interference is reduced, and meanwhile, the high-frequency voltage variation nodes are all provided with stratum copper-clad (middle layer) envelopes, so that the peak voltage of the high-frequency noise is greatly absorbed.

Inventors

• SANG QUAN
• LI YUQING
• DU MINJIE

Assignees

• 华东光电集成器件研究所

Dates

Publication Date

20260505

Application Date

20221130

Claims (1)

1. 1. A hybrid integrated low noise power circuit, comprising: a. The middle layer is provided with a stratum GND copper-clad, a group of high-frequency alternating current nodes L1-2 of the inductor L1 are arranged in a blank area of the stratum GND copper-clad, and the nodes L1-2 are communicated with the bottom layer; b. The top layer is provided with an inductor L1 and an SW end of a controller N1 of the inductor L1, the top layer is also provided with a node L1-1 connected with an input Vin, and the node L1-1 is connected with an input end of the inductor L1; c. The bottom layer is internally provided with a rectifier diode V1, the P pole of the rectifier diode V1 is correspondingly communicated with a node L1-2, the output end of the rectifier diode V1 is connected with a capacitor C3, and the other end of the capacitor C3 is connected with a GND copper-clad layer; The SW end of the inductor L1 is connected with the SW end of the N1 controller, the SW end is connected with the P end of the V1 rectifying diode of the stratum through the L1-2 node of the middle layer, the N end of the V1 rectifying diode is connected with the output end of the Vo, the output end of the Vo is connected with one end of the capacitor C3, the other end of the C3 capacitor is connected with the GND copper-clad layer, the GND copper-clad layer is connected with the GND of the N1 controller, and the GND copper-clad layer is connected with the input GND end.

Description

Hybrid integrated low-noise power circuit Technical Field The invention relates to the technical field of signal processing of mixed integrated circuit design, in particular to a mixed integrated low-noise power circuit. Background The hybrid integrated low-noise power circuit board is widely applied to the technical fields of signal processing, power supply design and the like. In a low-noise power circuit board, high-frequency power signal processing is often accompanied with large noise, and in order to reduce the noise, noise reduction design of the structural layout of the power circuit board is important in addition to noise reduction design in the aspect of circuit design. The invention discloses a power circuit board, which is shown in figure 1 and comprises pins, bonding wires, power chips, resistor chips, diodes, driving chips, grooves and plastic packages, and is characterized in that the grooves are formed between the devices, and three groups of power devices are respectively arranged in a T-shaped copper layer on the right side of the circuit board. The method has the beneficial effects that 1, under the condition of the same circuit board area and the same raw material, the flow direction of the solder paste is obviously and effectively blocked by the method for increasing the grooves, and the devices are positioned in a standard way and kept at a certain distance, so that the chips are not shorted any more. 2. Short circuit caused by solder paste overflowing to the surface of the chip is avoided, and the production efficiency is greatly improved. The invention is beneficial to the improvement of the production and processing efficiency of the power circuit, and does not relate to the optimization of circuit parameters. Through searching the existing patent searching tool, the utility model patent grant bulletin (patent grant bulletin CN 211295102U) of the layout structure of the gain-controllable low-noise amplifier, as shown in fig. 2, discloses the layout structure of the gain-controllable low-noise amplifier, which comprises a first layout region, a second layout region, a third layout region and a fourth layout region, wherein the first layout region, the third layout region and the fourth layout region are respectively connected with the second layout region, the first layout region is L-shaped, the second layout region and the third layout region are arranged on the inner side of the L-shaped in parallel, the second layout region is adjacent to two right-angle sides of the inner side of the L-shaped, the third layout region is adjacent to the right-angle sides of the inner side of the L-shaped, and a region is the fourth layout region at the right angle of the second layout region opposite to the inner side of the L-shaped. The utility model solves the problems of larger amplifier layout and weak anti-interference capability under the functions of controllable gain and low noise. The utility model is a semiconductor bare chip layout, and has different design fields with the hybrid integrated circuit layout of the utility model, and no specific noise reduction parameter design is adopted. The utility model discloses a layout structure of a radio frequency low noise amplifier, which is characterized by comprising a first layout area, a second layout area, a third layout area, a fourth layout area, a fifth layout area, a sixth layout area, a seventh layout area, an eighth layout area and a ninth layout area, wherein the second layout area and the third layout area are positioned at the center, the first layout area is positioned below the second layout area and the third layout area, the eighth layout area is positioned at the left of the second layout area, the ninth layout area is positioned at the right of the third layout area, and the sixth layout area is positioned above the eighth layout area and the second layout area. The first layout area, the second layout area and the sixth layout area form a signal path, and the fifth layout area, the ninth layout area, the second layout area and the eighth layout area form a power path. The utility model gives consideration to LNA performance, reasonably distributes signal paths, optimizes layout and reduces chip cost. The utility model is a semiconductor bare chip layout, which has different design fields with the hybrid integrated circuit layout of the utility model, and only the signal wiring is vertical to the power wiring, thus preventing the interference of the power supply to the signal and the design technology of reducing noise by the layout of the utility model. Disclosure of Invention The invention aims to provide a hybrid integrated low-noise power circuit, which achieves the purpose of reducing low noise by high-current output. The technical scheme adopted by the invention is as follows: A hybrid integrated low noise power circuit comprising: the middle layer midlayer1 is provided with a stratum GND copper-clad, a group of high-