CN-115797144-B - GPU drawing instruction buffer design method based on frame synchronization

Abstract

The invention discloses a GPU drawing instruction buffer design method based on frame synchronization, which comprises a first_BRAM memory, a second_BRAM memory, a THIRD _BRAM memory and a read-write controller, wherein a three-level buffer architecture is adopted, so that the problem that one frame of drawing instruction is disordered due to inconsistent speed of a CPU sending drawing instruction and a GPU reading drawing instruction is solved, and the integrity of each frame of drawing instruction is ensured; generating read-write address signals and control signals of the first_BRAM memory, the second_BRAM memory and the THIRD _BRAM memory by adopting a read-write controller; the invention can output the primitive drawing instruction and the character drawing instruction in parallel, and improves the GPU drawing efficiency.

Inventors

• SU LIN
• SUN ZHIWEI
• HAN MINGZHI

Assignees

• 中国航空工业集团公司洛阳电光设备研究所

Dates

Publication Date

20260508

Application Date

20221017

Claims (1)

1. 1. The GPU drawing instruction buffer design method based on frame synchronization is characterized by comprising the following steps of: The method comprises the steps that 1, a buffer system architecture comprises a first_BRAM memory, a second_BRAM memory, a THIRD _BRAM memory and a read-write controller, and a three-level buffer architecture is adopted; The first_BRAM memory stores the drawing instruction sent by the CPU, and when the first_BRAM memory receives the frame end mark, a frame of drawing instruction stored in the first_BRAM memory is continuously read out and written into the second_BRAM memory; when the SECOND_BRAM memory receives the frame start drawing mark, the CPU continuously reads out a frame of drawing instruction from the SECOND_BRAM memory, and divides the drawing instruction into a character drawing instruction and a primitive drawing instruction according to different drawing instruction command words, and writes the character drawing instruction and the primitive drawing instruction into the THIRD _BRAM memory; The THIRD _BRAM memory is divided into two parts for respectively storing the graphic primitive drawing instruction and the character drawing instruction, and the THIRD _BRAM memory reads the graphic primitive drawing instruction and the character drawing instruction in parallel and draws the graphic primitive drawing instruction and the character drawing instruction in parallel, so that the GPU drawing efficiency is improved; The read-write controller generates read-write address signals and control signals of the first_BRAM memory, the second_BRAM memory and the THIRD _BRAM memory; step 2, the clocks at the reading and writing ends of the first_BRAM memory are CPU_CLK, each frame of drawing instruction sent by the CPU is stored from the address 0 of the first_BRAM memory, when the CPU_WR_EN signal is valid, the drawing instruction is stored in the first_BRAM memory, and meanwhile, the bram1_wr_addr signal is added with 1; when the frame end mark signal is received, a frame of drawing instruction is sent, the bram1_wr_addr signal is cleared, the bram1_rd_addr signal is cleared, and the bram1_rd_en signal is valid; continuously reading a frame of drawing instruction from the first_BRAM memory every cycle by taking the CPU_CLK as a clock, and invalidating the bram1_rd_en signal; reading out a drawing instruction from the first_bram memory while the bram1_rd_addr signal is active, and adding 1 to the bram1_rd_addr signal; Step 3, the clocks at the reading and writing ends of the second_BRAM memory are CPU_CLK, and the drawing instruction read by the first_BRAM memory is stored into the second_BRAM memory according to the bram2_wr_en and bram2_wr_addr signals generated by the reading and writing controller; When receiving a frame start drawing mark signal, the GPU indicates that a new frame picture is to be drawn, the bram2_rd_en is effective, and the bram2_rd_addr signal is cleared, and after a frame drawing instruction is continuously read out from a SECOND_BRAM memory every cycle by taking a CPU_CLK as a clock, the bram2_rd_en signal is ineffective; The THIRD_BRAM memory is divided into two parts, and a graphic element drawing instruction and a character drawing instruction are respectively stored, wherein the graphic element drawing instruction comprises a line drawing instruction, a hollow circle drawing instruction, a filled circle drawing instruction and an arc drawing instruction; the drawing instructions read out by the second_bram memory divide the drawing instructions into character drawing instructions and primitive drawing instructions according to different drawing instruction command words; Step 5, the writing clock of the THIRD_BRAM memory is CPU_CLK, the reading clock is GPU_CLK, and the graphic primitive drawing instruction and the character drawing instruction read by the SECOND_BRAM memory are respectively stored in the corresponding parts of the THIRD _BRAM memory according to the bram3_wr_en and the bram3_wr_addr signals generated by the read-write controller; When the GPU_RD_EN signal is received, the BRAM3_rd_addr signal is added with 1, a primitive drawing instruction and a character drawing instruction are read in parallel from a THIRD _BRAM memory and sent to the GPU for drawing; And step 6, the read-write controller can monitor the use depth of the first_BRAM memory, and when the CPU sends a frame of drawing instruction abnormality to cause the number of the drawing instructions to exceed the maximum depth of the first_BRAM memory, the read-write controller can generate a memory overflow flag signal and send the memory overflow flag signal to the CPU for fault reporting.

Description

GPU drawing instruction buffer design method based on frame synchronization Technical Field The invention belongs to the technical field of graphic drawing, and particularly relates to a GPU drawing instruction buffer design method. Background In the graphics drawing process, a CPU generally sends a drawing instruction, and a GPU receives the corresponding drawing instruction to draw a graphic. Because the rate of sending the drawing instruction by the CPU is inconsistent with the rate of reading the drawing instruction by the GPU, a frame of drawing instruction is disordered. Therefore, the design can ensure that the GPU drawing instruction buffer which outputs the complete drawing instructions of each frame becomes the premise of correctly drawing the graphics. Disclosure of Invention In order to overcome the defects of the prior art, the invention provides a frame synchronization-based GPU drawing instruction buffer design method, which comprises a first_BRAM memory, a second_BRAM memory, a THIRD _BRAM memory and a read-write controller, wherein a three-level buffer architecture is adopted, so that the problem that a frame drawing instruction is disordered due to inconsistent speed of a CPU sending drawing instruction and a GPU reading drawing instruction is solved, the integrity of each frame drawing instruction is ensured, the read-write controller is adopted to generate read-write address signals and control signals of the first_BRAM memory, the second_BRAM memory and the THIRD _BRAM memory, and the invention can output the graphic drawing instruction and the character drawing instruction in parallel, thereby improving the drawing efficiency of the GPU. The technical scheme adopted by the invention for solving the technical problems comprises the following steps: The method comprises the steps that 1, a buffer system architecture comprises a first_BRAM memory, a second_BRAM memory, a THIRD _BRAM memory and a read-write controller, and a three-level buffer architecture is adopted; The first_BRAM memory stores the drawing instruction sent by the CPU, and when the first_BRAM memory receives the frame end mark, a frame of drawing instruction stored in the first_BRAM memory is continuously read out and written into the second_BRAM memory; when the SECOND_BRAM memory receives the frame start drawing mark, the CPU continuously reads out a frame of drawing instruction from the SECOND_BRAM memory, and divides the drawing instruction into a character drawing instruction and a primitive drawing instruction according to different drawing instruction command words, and writes the character drawing instruction and the primitive drawing instruction into the THIRD _BRAM memory; The THIRD _BRAM memory is divided into two parts for respectively storing the graphic primitive drawing instruction and the character drawing instruction, and the THIRD _BRAM memory reads the graphic primitive drawing instruction and the character drawing instruction in parallel and draws the graphic primitive drawing instruction and the character drawing instruction in parallel, so that the GPU drawing efficiency is improved; The read-write controller generates read-write address signals and control signals of the first_BRAM memory, the second_BRAM memory and the THIRD _BRAM memory; step 2, the clocks at the reading and writing ends of the first_BRAM memory are CPU_CLK, each frame of drawing instruction sent by the CPU is stored from the address 0 of the first_BRAM memory, when the CPU_WR_EN signal is valid, the drawing instruction is stored in the first_BRAM memory, and meanwhile, the bram1_wr_addr signal is added with 1; when the frame end mark signal is received, a frame of drawing instruction is sent, the bram1_wr_addr signal is cleared, the bram1_rd_addr signal is cleared, and the bram1_rd_en signal is valid; continuously reading a frame of drawing instruction from the first_BRAM memory every cycle by taking the CPU_CLK as a clock, and invalidating the bram1_rd_en signal; reading out a drawing instruction from the first_bram memory while the bram1_rd_addr signal is active, and adding 1 to the bram1_rd_addr signal; Step 3, the clocks at the reading and writing ends of the second_BRAM memory are CPU_CLK, and the drawing instruction read by the first_BRAM memory is stored into the second_BRAM memory according to the bram2_wr_en and bram2_wr_addr signals generated by the reading and writing controller; When receiving a frame start drawing mark signal, the GPU indicates that a new frame picture is to be drawn, the bram2_rd_en is effective, and the bram2_rd_addr signal is cleared, and after a frame drawing instruction is continuously read out from a SECOND_BRAM memory every cycle by taking a CPU_CLK as a clock, the bram2_rd_en signal is ineffective; The THIRD_BRAM memory is divided into two parts, and a graphic element drawing instruction and a character drawing instruction are respectively stored, wherein the graphic element drawing instructi