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CN-115810594-B - Semiconductor three-dimensional packaging structure with vapor chamber

CN115810594BCN 115810594 BCN115810594 BCN 115810594BCN-115810594-B

Abstract

The invention provides a semiconductor three-dimensional packaging structure with a vapor chamber, wherein a cover is combined with a bottom plate to enclose the vapor chamber, and a plurality of medium layer stacked three-dimensional structures for disposing semiconductor wafers are packaged in the vapor chamber. The inner side of the cover forms a group of capillary structures, and a group of nets are combined with the inner side of the cover and shield the group of capillary structures. Each interposer has a set of protrusions on its periphery, two protrusions being spaced apart by a recess, all of the interposers contacting the set of webs with the protrusions, the recesses from the upper interposer to the lower interposer being a flow path to the vapor chamber. And a proper amount of cooling fluid is added into the vapor chamber, and the cooling fluid is subjected to liquid-state to gaseous state conversion thermal circulation from the runner to the group of capillary structures, so that the heat dissipation effect of the semiconductor wafer is achieved. The top and bottom surfaces of each interposer also have capillary structures that direct the high temperature gases of the two interposers to the vapor chamber via the flow channels as part of the thermal cycle.

Inventors

  • WU ZHIMENG

Assignees

  • 创新服务股份有限公司

Dates

Publication Date
20260505
Application Date
20210915

Claims (9)

  1. 1.A semiconductor three-dimensional package structure having a vapor chamber, comprising: A base plate; The semiconductor chips are stacked on the bottom plate through a plurality of medium layers, the medium layers are provided with a top surface capillary structure and a bottom surface capillary structure, the periphery of the medium layers is provided with a group of convex parts, and the two convex parts are separated by a concave part; A lid having a set of capillary structures and a set of webs on the inside thereof, the set of webs shielding the capillary structures, the lid enclosing a vapor chamber when the lid is combined with the base plate, the lid enclosing all semiconductor wafers, all intermediaries contacting the set of webs with protrusions, the recesses from the upper intermediaries to the lower intermediaries forming a flow path to the vapor chamber, and And a proper amount of cooling fluid is added into the vapor chamber, and liquid-state to gaseous heat circulation is performed among the group of capillary structures, the group of flow channels, the top surface capillary structure and the bottom surface capillary structure, so that the heat dissipation effect of the semiconductor wafer is achieved.
  2. 2. The semiconductor package structure of claim 1, wherein the recesses of the upper interposer to the lower interposer are staggered to maintain inclined flow paths such that the protrusions of the upper interposer to the lower interposer are arranged in a stepped configuration.
  3. 3. The semiconductor package according to claim 1, wherein the lid is made of one of copper, copper alloy and other heat conductive metals.
  4. 4. The semiconductor package according to claim 1, wherein one of copper, copper alloy and other heat conductive metals is coated on the surface of the lid.
  5. 5. The semiconductor package according to claim 1, wherein the plurality of capillary structures are staggered slots formed in the surface of the lid by one of etching, laser engraving, stamping and die casting.
  6. 6. The semiconductor package according to claim 1, wherein the cooling fluid is selected from the group consisting of ultrapure water, ethanol, butane, and mixtures thereof.
  7. 7. The semiconductor package according to claim 1, wherein the interposer is a ceramic substrate.
  8. 8. The semiconductor package according to claim 1, wherein a set of thermally conductive pillars are arrayed across all stacked interposer layers.
  9. 9. The semiconductor package according to claim 1, wherein the cover has a plurality of heat dissipation fins bonded to an outer portion thereof.

Description

Semiconductor three-dimensional packaging structure with vapor chamber Technical Field The present invention relates to semiconductor packaging technology, and more particularly to a three-dimensional packaging structure that utilizes vapor chambers or temperature equalization structures to generate heat dissipation effects for semiconductor chips. Background More semiconductor wafers are gathered together by adopting a three-dimensional packaging structure, so that the requirements of small volume and strong functions are met. After power-on, the semiconductor chip generates high heat, which delays the operation efficiency and even reduces the lifetime. How to dissipate heat is a challenge for semiconductor chips. In the patent 20200105644, a heat sink is attached to a semiconductor package structure, and cooling liquid with a low temperature is continuously supplied to a flow channel to take away heat of the package structure. Although, the design of the water cooling mode can improve the heat dissipation efficiency. However, the force of the heat sink pushing the cooling fluid flow comes from a pump, and the heat sink is huge, which obviously cannot keep up with the advanced technology of miniaturization of the package structure. The taiwan 202121618 patent proposes a stacked structure, and combines with the heat dissipation structure of the taiwan 202002201 patent, and adds a heat conduction structure inside the three-dimensional package to improve the heat dissipation problem. Specifically, each layer of the semiconductor chip stack is additionally provided with a heat dissipation layer, the heat dissipation layer is made of a thermal interface material with heat conduction efficiency, and the heat conduction effect of the semiconductor chip is obtained through an electrical connection structure such as a through silicon via or a copper column. The disadvantage is that the heat conduction and dissipation effect is limited. Particularly, when the layers are stacked, the heat dissipation of the lower semiconductor chip is not good, and the effect is greatly reduced. The scheme for solving the heat dissipation problem is a vapor chamber structure or a temperature equalizing structure. The steam chamber structure utilizes the thermal circulation of the gas phase and the liquid phase of the cooling fluid to achieve the rapid heat dissipation effect. Therefore, the vapor chamber is applied to the three-dimensional packaging technology of the semiconductor, and can improve the heat dissipation efficiency of a plurality of high-performance chips. For example, japanese patent No. 5554444 (publication No. 2015050323) and taiwan patent No. 202002031 both refer to a cover body, which is applied to a three-dimensional package structure of a semiconductor to realize the heat dissipation effect of a vapor chamber. In addition, in taiwan patent No. I672775 (application No. 106119235), at least one cooling channel is designed around the stacked semiconductor chips in the three-dimensional package structure. The fluid phase-changed in the cooling channel takes away the heat of the semiconductor wafer to have a heat dissipation effect, so the cooling channel is equivalent to the function of a vapor chamber. There is also a semiconductor package structure and an assembly structure, in which a vapor chamber is provided between a semiconductor wafer and a package substrate, the vapor chamber takes away heat of the semiconductor wafer, and patent applications such as U.S. 20200111728 and chinese 111009493 are filed to multiple countries. In the above vapor chamber patents, the vapor chamber structure is indirectly bonded to the semiconductor package structure by using the thermal interface material or the encapsulant as a medium. Thus, the heat conductivity of the medium greatly influences the heat dissipation effect of the vapor chamber structure. In addition, the disclosure of U.S. patent No. 20190393193 discloses a semiconductor package having a vapor chamber function, which is disposed between a plurality of integrated circuits, mainly in a space of an electrical connection structure. However, the flow space of the vapor chamber is limited by the narrow space of the integrated circuit, which results in poor heat dissipation efficiency of the semiconductor package as a whole. Still another semiconductor package has an interposer attached to the semiconductor, as disclosed in U.S. patent No. 7,002,247. Wherein the interposer has two plates comprising a core structure such as a recess, and the internal sealed volume of the interposer is in direct contact with the back surface of the semiconductor, thereby forming a vapor chamber in an attempt to reduce the heat of the semiconductor wafer for a uniform temperature effect. Unfortunately, the semiconductor package is prone to damage to the semiconductor wafer by virtue of the attachment structure on the wafer surface alone, relatively weakening the overall support structure. D