CN-115826718-B - Power-on reset circuit

CN115826718BCN 115826718 BCN115826718 BCN 115826718BCN-115826718-B

Abstract

The invention discloses a power-on reset circuit which comprises a feedback voltage dividing unit connected between a first power supply and a second power supply, wherein one of the first power supply and the second power supply is a power supply voltage, the feedback voltage dividing unit is used for dividing the power supply voltage to generate a first sampling voltage and a second sampling voltage, the comparison unit comprises a first transistor and a second transistor, one end of the first transistor and one end of the second transistor are connected with the second power supply, the control end of the first transistor is connected with the first sampling voltage and is used for generating a first current according to the first sampling voltage, the control end of the second transistor is connected with the second sampling voltage and is used for generating a second current according to the second sampling voltage, the first current and the second current are compared at a comparison node, and a shaping unit is connected with the comparison node and is used for shaping the voltage of the comparison node to output a reset signal, so that the problem that the traditional power-on reset circuit is sensitive to temperature is effectively solved, and false triggering in the chip power-on process is avoided.

Inventors

ZHANG QINGYA
WEI MENGZHAO

Assignees

杭州深谙微电子科技有限公司

Dates

Publication Date: 20260508
Application Date: 20221018

Claims (6)

1. A power-on reset circuit, comprising: The feedback voltage dividing unit is connected between a first power supply and a second power supply, one of the first power supply and the second power supply is a power supply voltage, the feedback voltage dividing unit is used for dividing the power supply voltage to generate a first sampling voltage and a second sampling voltage, the feedback voltage dividing unit comprises a first resistor, a second resistor and a third transistor which are sequentially connected between the first power supply and the second power supply, one end of the second resistor, which is close to the third transistor, is used for outputting the first sampling voltage, one end of the second resistor, which is far away from the third transistor, is used for outputting the second sampling voltage, and the control end of the third transistor is connected with the second sampling voltage; The comparison unit comprises a first transistor and a second transistor, wherein the size ratio of the first transistor to the second transistor to the third transistor is m:1, m is an integer larger than 1, the first transistor, the second transistor and the third transistor work in a subthreshold region, one ends of the first transistor and the second transistor are connected with a second power supply, the control end of the first transistor is connected with a first sampling voltage and is used for generating a first current according to the first sampling voltage, the control end of the second transistor is connected with a second sampling voltage and is used for generating a second current according to the second sampling voltage, the comparison unit further comprises a current mirror structure and is used for mirroring the second current to a branch where the first current is located, a comparison node is located in the branch where the first current is located, the first current and the second current are compared at the comparison node, and And the shaping unit is connected with the comparison node and is used for shaping the voltage of the comparison node to output a reset signal.
2. The power-on reset circuit of claim 1, wherein the current mirror structure comprises a fourth transistor and a fifth transistor, Sources of the fourth transistor and the fifth transistor are connected to the first power supply, The gates of the fourth and fifth transistors are connected to each other, and to the drain of the fifth transistor, The drain of the fourth transistor is connected with the branch of the first current, and the drain of the fifth transistor is connected with the branch of the second current.
3. The power-on reset circuit of claim 2, wherein the first transistor, the second transistor, and the third transistor are NMOS transistors or NPN transistors, the voltage of the first power supply is a power supply voltage, and the voltage of the second power supply is a ground voltage.
4. A power-on reset circuit as claimed in claim 3, wherein the fourth and fifth transistors are PMOS transistors.
5. The power-on reset circuit of claim 2, wherein the first transistor, the second transistor, and the third transistor are PMOS transistors or PNP transistors, the voltage of the first power supply is a ground voltage, and the voltage of the second power supply is a power supply voltage.
6. The power-on reset circuit of claim 5, wherein the fourth transistor and the fifth transistor are NMOS transistors.

Description

Power-on reset circuit Technical Field The invention relates to the technical field of integrated circuits, in particular to a power-on reset circuit. Background With the increasing integration of chips, in a System on Chip (SoC) integrated circuit design, more and more functions are integrated on a single Chip. A Power-On-Reset circuit (POR) is an indispensable component in the SoC. In the initial stage of starting the whole system, the stability of circuits in the chip is required to be maintained, the phenomenon that logic loops are disordered in the circuits in the chip are prevented from occurring in the power voltage rising process, a power-on reset circuit provides a power-on reset signal in the chip to ensure that the system can be started normally, in the normal working stage of the system, if the power voltage is too low, the power-on reset signal can be reset automatically, in the power voltage rising process, the power-on reset signal is kept at a low level all the time until the power voltage rises to a normal working voltage, and then the power-on reset signal can be turned to a high level rapidly. At this time, the chip starts to initialize, and before the initialization is completed, the devices inside the chip ignore external signals (including transmitting data, etc.), and only the reset pin is internally gated by the POR signal, so as to realize the initialization. However, the semiconductor device in the existing power-on reset circuit is sensitive to temperature change, so that the output signal of the power-on reset circuit changes along with the temperature change, and the IC chip is easy to be erroneously converted from a reset state to a working state, and the IC chip cannot work normally. Disclosure of Invention Therefore, the invention aims to provide the zero-temperature-drift power-on reset circuit, which effectively solves the problem that the traditional power-on reset circuit is sensitive to temperature, avoids false triggering in the power-on process of a chip, and ensures that the chip can be effectively reset after power-on. According to the embodiment of the invention, a power-on reset circuit is provided, which comprises a feedback voltage dividing unit connected between a first power supply and a second power supply, wherein one of the first power supply and the second power supply is a power supply voltage, the feedback voltage dividing unit is used for dividing the power supply voltage to generate a first sampling voltage and a second sampling voltage, a comparison unit comprises a first transistor and a second transistor, one ends of the first transistor and the second transistor are connected with the second power supply, a control end of the first transistor is connected with the first sampling voltage and is used for generating a first current according to the first sampling voltage, a control end of the second transistor is connected with the second sampling voltage and is used for generating a second current according to the second sampling voltage, the first current and the second current are compared at a comparison node, and a shaping unit is connected with the comparison node and is used for shaping the voltage of the comparison node to output a reset signal. Optionally, the feedback voltage dividing unit comprises a first resistor, a second resistor and a third transistor which are sequentially connected between the first power supply and the second power supply, wherein one end of the second resistor, which is close to the third transistor, is used for outputting the first sampling voltage, one end of the second resistor, which is far away from the third transistor, is used for outputting the second sampling voltage, and the control end of the third transistor is connected with the second sampling voltage. Optionally, the size ratio of the first transistor, the second transistor and the third transistor is m:1:1, wherein m is an integer greater than 1. Optionally, the first transistor, the second transistor, and the third transistor operate in a subthreshold region. Optionally, the comparing unit further includes a current mirror structure for mirroring the second current to a branch where the first current is located, and the comparing node is located in the branch where the first current is located. Optionally, the current mirror structure includes a fourth transistor and a fifth transistor, sources of the fourth transistor and the fifth transistor are connected to the first power source, gates of the fourth transistor and the fifth transistor are connected to each other and to a drain of the fifth transistor, a drain of the fourth transistor is connected to the branch of the first current, and a drain of the fifth transistor is connected to the branch of the second current. Optionally, the first transistor, the second transistor and the third transistor are NMOS transistors or NPN transistors, a voltage of the first power supply is a power supply voltag