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CN-115828838-B - Reinforced memory design method, system, device and storage medium

CN115828838BCN 115828838 BCN115828838 BCN 115828838BCN-115828838-B

Abstract

The invention discloses a method, a system, a device and a storage medium for designing a reinforced memory, which relate to the technical field of memory system design and comprise a 6U board card, FT2000+/64 main chips and other components which are arranged on the 6U board card, wherein the memory is arranged by adopting surface-mounted memory particles, 8 channels of a CPU are used, each channel is a Rank, each Rank is provided with 8 memory particles which are respectively 4 memory particles on the front side and 4 memory particles on the back side, for each Rank, a data signal is directly connected to the 8 memory particles by each chip pin of the CPU, the signal is sent by the CPU, and a serial mode is adopted to pass through each memory chip. The invention is based on the Feiteng platform FT2000 < + >/64 main chip 6U board card design, can fully utilize 8 memory channels of the main chip, and optimizes the signal integrity, thereby improving the memory frequency and the total bandwidth of the memory.

Inventors

  • LI HUA
  • WANG TING
  • ZHOU SHENGRUI
  • YU HONGYANG

Assignees

  • 西安超越申泰信息科技有限公司

Dates

Publication Date
20260512
Application Date
20221216

Claims (8)

  1. 1. A reinforced memory design method is characterized by comprising a 6U board card, a FT2000+/64 main chip and other components which are arranged on the 6U board card, wherein memory arrangement is carried out by adopting surface-mounted memory particles, 8 channels of a CPU are used, and each channel is provided with a Rank, each Rank is provided with 8 memory particles, namely 4 memory particles on the front side and 4 memory particles on the corresponding back side; For each Rank, a data signal is directly connected to the 8 memory particles by each chip pin of the CPU, the signal is sent out by the CPU and passes through each memory chip in a serial mode; The 8 ranks are symmetrically and uniformly distributed on the left side and the right side of the CPU, and 4 ranks on one side are arranged in two rows and two columns, and each Rank consists of 4 memory particles on the front side which are vertically arranged and 4 memory particles on the back side which are vertically arranged corresponding to the front side; The signal paths of the 8 memory particles of each Rank sequentially pass through the adjacent memory particles from the first memory particle to the last memory particle.
  2. 2. The method for designing a reinforced memory according to claim 1, wherein the 6U-board card is fixed at 233.35 x 160mm, the installation space of the memory area is not more than 145 x 74mm, the CPU occupies 61 x 61mm, and memory particles are placed in the remaining space on each of the left and right sides of the CPU.
  3. 3. The method for designing a reinforced memory according to claim 1 or 2, wherein the other components include a BMC management module, an X100 bridge chip, a tera chip, a power module, and an FPGA chip.
  4. 4. The method of claim 3, wherein the signals sent by the CPU include address signals, control signals, and command signals.
  5. 5. The method for designing a reinforced memory according to claim 1, each memory granule is characterized by having 11 signal connection pins.
  6. 6. The reinforced memory system is characterized by comprising a 6U board card, a FT2000+/64 main chip, other components and surface-mounted memory particles, wherein the FT2000+/64 main chip is arranged on the 6U board card; 8 channels of the CPU are used, each channel is provided with a Rank, and each Rank is provided with 8 memory particles, namely 4 memory particles on the front side and 4 memory particles on the corresponding back side; For each Rank, a data signal is directly connected to the 8 memory particles by each chip pin of the CPU, the signal is sent out by the CPU and passes through each memory chip in a serial mode; The 8 ranks are symmetrically and uniformly distributed on the left side and the right side of the CPU, and 4 ranks on one side are arranged in two rows and two columns, and each Rank consists of 4 memory particles on the front side which are vertically arranged and 4 memory particles on the back side which are vertically arranged corresponding to the front side; The signal paths of the 8 memory particles of each Rank sequentially pass through the adjacent memory particles from the first memory particle to the last memory particle; The memory system is arranged by the reinforced memory design method as claimed in any one of claims 1 to 5.
  7. 7. An electronic device, comprising: A processor; the DDR memory system of claim 6, wherein the DDR memory system is electrically coupled to the processor.
  8. 8. A DDR storage medium, comprising: A PCB substrate; The memory system power supply module is arranged on the PCB substrate; the DDR memory particles are respectively and regularly arranged on the front surface and the back surface of the PCB substrate; all the DDR memory particles and the processor end adopt the reinforced memory design method as in any one of claims 1 to 5 for circuit wiring.

Description

Reinforced memory design method, system, device and storage medium Technical Field The invention relates to the technical field of memory system design, in particular to a method, a system, a device and a storage medium for designing a reinforced memory. Background In the special fields of coping with mountain, mine, oilfield, battlefield and the like and petroleum, geological exploration and the like, especially in the vehicle-mounted vibration-resistant scene of the field for a long time and a long distance, the common DIMM slot type memory strip is easy to loosen or be polluted, thereby causing system faults; In the past ten years, with the unprecedented development of the fields of programs and applications, large data sets, 3D model rendering, cloud platforms and the like, the requirements on the system memory are increasing. With the increasing number of CPU cores, memory technology needs to be further extended to cope with these massive demands. Higher dominant frequency and higher bandwidth memory is the best solution to achieve the currently required performance. Therefore, the design of the memory system is necessary to ensure that the memory can work at the maximum design rate, so as to meet the highest memory access requirement of the data processing of the processor. Disclosure of Invention The technical task of the invention is to provide a method, a system, a device and a storage medium for designing a reinforced memory, which optimize signal integrity so as to improve the memory frequency and the total bandwidth of the memory. The technical scheme adopted for solving the technical problems is as follows: A reinforced memory design method comprises a 6U board card, a FT2000+/64 main chip and other components which are arranged on the 6U board card, wherein memory arrangement is carried out by adopting surface-mounted memory particles, 8 channels of a CPU are used, and each channel is provided with one Rank, each Rank is provided with 8 memory particles, namely 4 memory particles on the front side and 4 memory particles on the corresponding back side; for each Rank, the data signal is directly connected to the 8 memory particles by each chip pin of the CPU, the signal is sent by the CPU, and a serial mode is adopted to pass through each memory chip to ensure that no signal is branched. The method provides a reinforced high-main-frequency, high-bandwidth and extremely space-saving memory system design method based on surface-mounted memory particles, and a reinforced high-performance extremely space-saving memory storage system is designed based on the FT2000+/64 main chip 6U (233.35 x 160 mm) board card design and combining the application requirements and the localization requirements of the current data center products. Further, the size of the 6U-plate card is fixed to 233.35 x 160mm, the installation space of the memory area is not more than 145 x 74mm, the CPU occupies 61 x 61mm, and memory particles are placed on each of the left side and the right side of the CPU in the remaining space. Because the installation space of the memory area is not more than 145 x 74mm, the CPU occupies 61 x 61mm, and the rest space only allows two rows of memory particles to be placed on one side of the CPU, and according to the traditional design method, the CPU is respectively placed with two rows of memory particles left and right, so that only four memory channels of the CPU can be utilized. The FT2000+/64 supports 8 memory channels, each memory channel at least needs 8 memory particles, each particle is 8 bits, the traditional design method calculates according to 8 particles of a Rank, the total bit width is 64 bits, only 32 memory particles can be placed, and the bit width of four channels is 256 bits, so that waste is caused, the memory capacity is low, the total bandwidth is not increased, and the performance of a CPU cannot be exerted. If a dual Rank design is used, i.e. the front and back of the memory is pasted, the signal mode is one-to-two, so that although 64 particles can be placed and the memory capacity can be maximized, the dual Rank mode memory only selects a single Rank to work according to a CS signal chip selection once, and still cannot guarantee that all memory particles work simultaneously, the total bit width at the same moment is still 256 bits, and the total memory bandwidth is limited. Meanwhile, at least 8 memory particles need to be arranged on the same surface and the same Rank in the traditional design, all the particles are further branched because of signals, and the particles at the nearest end are reflected by the signals more seriously, so that the signal quality is affected, the DDR main frequency is reduced, and the total bandwidth of a memory system is affected. Further, the 8 ranks are symmetrically and uniformly distributed on the left side and the right side of the CPU, 4 ranks on one side are arranged in two rows and two columns, and each Rank is composed of 4 me