CN-115831191-B - Three-dimensional memory device

Abstract

The present disclosure provides a three-dimensional memory device, such as a three-dimensional AND gate flash memory device. The three-dimensional memory device includes a plurality of memory cell arrays, a plurality of bit line switches, and a plurality of source line switches. The memory cell array has a plurality of memory cell columns respectively coupled to a plurality of source lines and a plurality of bit lines. The bit line switch and the source line switch are respectively composed of a plurality of first transistors and second transistors. The first transistor is coupled to a common bit line and a bit line. The second transistor is coupled to the common source line and the source line. The first transistor is a P-type transistor or an N-type transistor with a triple-well substrate, and the second transistor is a P-type transistor or an N-type transistor with a triple-well substrate.

Inventors

• LIN YONGFENG
• LUO SIJUE
• YE TENGHAO
• LV HANTING

Assignees

• 旺宏电子股份有限公司

Dates

Publication Date

20260508

Application Date

20210929

Priority Date

20210916

Claims (19)

1. 1. A three-dimensional memory device, comprising: A plurality of memory cell arrays having a corresponding plurality of memory cell columns coupled to the plurality of source lines and the plurality of bit lines, respectively; A plurality of bit line switches each composed of a plurality of first transistors having first ends coupled to a common bit line and second ends coupled to the bit lines, respectively A plurality of source line switches respectively composed of a plurality of second transistors, the first ends of the second transistors are coupled to a common source line, the second ends of the second transistors are respectively coupled to the source lines, The first transistors are P-type transistors or N-type transistors with triple-well substrates, and the second transistors are P-type transistors or N-type transistors with triple-well substrates; When the second transistors are N-type transistors with triple well substrates, each of the second transistors includes: An N-type deep well region; a P-type well region formed on the N-type deep well region; an N-type well region formed at the side of the P-type well region; A first N-type heavily doped region, a second N-type heavily doped region and a P-type heavily doped region formed on the P-type well region, wherein the first N-type heavily doped region and the second N-type heavily doped region form a channel, the P-type heavily doped region is used for receiving a bias voltage, the first N-type heavily doped region, the second N-type heavily doped region and the P-type heavily doped region are isolated by an insulation structure, and And a gate structure formed on the first N-type heavily doped region, the second N-type heavily doped region and the channel.
2. 2. The three-dimensional memory device of claim 1, wherein the first transistors are controlled by first select signals to be turned on or off and the second transistors are controlled by second select signals to be turned on or off.
3. 3. The three-dimensional memory device of claim 1, wherein on/off states of each of the bit line switches and each of the source line switches corresponding to the same memory cell row are the same.
4. 4. The three-dimensional memory device of claim 1, wherein the memory cell arrays are divided into memory cell columns that respectively receive word line signals.
5. 5. The three-dimensional memory device of claim 4, wherein in the read operation, a selected bitline switch corresponding to a selected memory cell is turned on and provides a first voltage to the selected memory cell, and a selected source line switch corresponding to the selected memory cell is turned on and provides a second voltage to the selected memory cell, wherein the first voltage is greater than the second voltage.
6. 6. The three-dimensional memory device of claim 4, wherein each of the first transistor and each of the second transistors is an N-type transistor having a triple well substrate, and in the programming operation, a selected bit line switch corresponding to a selected memory cell is turned on and provides a first voltage having a negative value to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, a remaining plurality of unselected source line switches are turned on and provide a second voltage having a positive value to the plurality of unselected memory cells, a third voltage having a positive value corresponding to a selected character signal of the selected memory cell, and a fourth voltage having a negative value corresponding to a remaining plurality of unselected character signals.
7. 7. The three-dimensional memory device of claim 4, wherein each of the first transistor and each of the second transistors is an N-type transistor having a triple well substrate, a selected bit line switch corresponding to a selected memory cell is turned on and provides a first voltage having a positive value to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, a plurality of unselected source line switches are turned on and provide a second voltage having a negative value to the plurality of unselected memory cells, a third voltage having a negative value of selected character signals corresponding to the selected memory cell, and a fourth voltage having a positive value of unselected character signals in the word line signals.
8. 8. The three-dimensional memory device of claim 4, wherein each of the first transistor and each of the second transistor is an N-type transistor having a triple well substrate, and wherein during a block erase operation, the bit line switches and the source line switches are turned on and respectively provide a first voltage to the memory cells that is positive, a second voltage that is negative for a plurality of selected word signals of a selected memory cell block, and a third voltage that is positive for a plurality of selected word signals of at least one unselected memory cell block.
9. 9. The three-dimensional memory device of claim 4, wherein each of the first transistors is an N-type transistor having a triple well substrate, each of the second transistors is a P-type transistor, a selected bit line switch corresponding to a selected memory cell is turned on and provides a first voltage having a negative value to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, a plurality of unselected source line switches are turned on and provide a second voltage having a positive value to a plurality of unselected memory cells, a third voltage having a positive value corresponding to a selected word signal of the selected memory cell, and a fourth voltage having a negative value corresponding to a plurality of unselected word signals.
10. 10. The three-dimensional memory device of claim 4, wherein each of the first transistors is an N-type transistor having a triple well substrate, each of the second transistors is a P-type transistor, a selected bitline switch corresponding to a selected memory cell is turned off, a plurality of unselected bitline switches are turned on and provide a negative first voltage to a plurality of unselected memory cells, a selected source line switch corresponding to the selected memory cell is turned on and provides a positive second voltage to the selected memory cell, a third voltage corresponding to a selected word signal of the selected memory cell is negative, and a plurality of unselected word signals are positive fourth voltages during a byte erase operation.
11. 11. The three-dimensional memory device of claim 4, wherein each of the first transistors is an N-type transistor having a triple well substrate, each of the second transistors is a P-type transistor, and the bit line switches and the source line switches are turned on and respectively provide a first voltage having a positive value to the memory cells, a second voltage having a negative value corresponding to a plurality of selected word signals of a selected memory cell block, and a third voltage having a positive value corresponding to a plurality of selected word signals of at least one unselected memory cell block during a block erase operation.
12. 12. The three-dimensional memory device of claim 4, wherein each of the first transistors is a P-type transistor, each of the second transistors is an N-type transistor having a triple well substrate, a selected bitline switch corresponding to a selected memory cell is turned on and provides a first voltage of positive value to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned on and provides a second voltage of negative value to the selected memory cell, and the wordline signals correspond to a third voltage of positive value of a selected character signal of the selected memory cell and a fourth voltage of negative value of a plurality of unselected character signals.
13. 13. The three-dimensional memory device of claim 4, wherein each of the first transistors is a P-type transistor, each of the second transistors is an N-type transistor having a triple well substrate, in a byte erase operation, a selected bitline switch corresponding to a selected memory cell is turned on and provides a first voltage having a positive value to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, a plurality of unselected source line switches are turned on and provide a second voltage having a negative value to a plurality of unselected memory cells, and among the wordline signals, a selected character signal corresponding to the selected memory cell is a third voltage having a negative value, and a plurality of unselected character signals are fourth voltages having a positive value.
14. 14. The three-dimensional memory device of claim 4, wherein each of the first transistors is a P-type transistor, each of the second transistors is an N-type transistor having a triple well substrate, and during a block erase operation, the bit line switches and the source line switches are turned on and respectively provide a first voltage to the memory cells that is positive, a second voltage that is negative for a plurality of selected word signals of a selected memory cell block, and a third voltage that is positive for a plurality of selected word signals of at least one unselected memory cell block.
15. 15. The three-dimensional memory device of claim 4, wherein the first transistors and the second transistors are P-type transistors, and in the programming operation, a selected bit line switch corresponding to a selected memory cell is turned on and provides a first voltage having a negative value to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, a plurality of unselected source line switches are turned on and provide a second voltage having a positive value to a plurality of unselected memory cells, and the word line signals have a third voltage having a positive value corresponding to a selected character signal of the selected memory cell and a fourth voltage having a negative value corresponding to a plurality of unselected character signals.
16. 16. The three-dimensional memory device of claim 4, wherein the first transistors and the second transistors are P-type transistors, a selected bit line switch corresponding to a selected memory cell is turned on and provides a first voltage having a positive value to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, a plurality of unselected source line switches are turned on and provide a second voltage having a negative value to the plurality of unselected memory cells, a third voltage having a negative value corresponding to a selected character signal of the selected memory cell, and a fourth voltage having a positive value among the plurality of unselected character signals.
17. 17. The three-dimensional memory device of claim 4, wherein the first transistors and the second transistors are P-type transistors, and the bit line switches and the source line switches are turned on and respectively provide a first voltage with positive values to the memory cells, a second voltage with negative values corresponding to the selected character signals of a selected memory cell block, and a third voltage with positive values corresponding to the selected character signals of at least one unselected memory cell block during the block erase operation.
18. 18. The three-dimensional memory device of claim 1, wherein the memory cell arrays are and gate flash memory cell arrays.
19. 19. The three-dimensional memory device of claim 1, wherein each of the source lines is coupled to the common source line only through a corresponding one of the source line switches, and each of the bit lines is coupled to the common bit line only through a corresponding one of the bit line switches.

Description

Three-dimensional memory device Technical Field The present disclosure relates to a three-dimensional memory device, and more particularly, to a three-dimensional memory device that can provide a negative source line voltage or bit line voltage. Background With the progress of semiconductor technology and the refinement of functions of electronic products, it is becoming a trend to provide highly dense flash memories on electronic products. In existing three-dimensional and gate flash memory devices, the bit line switch and the source line switch are often implemented by N-type transistors. In such a case, the bit line switch and the source line switch can only provide the word line voltage and the source line voltage with positive values to the memory cell, and cause the memory cell to perform a program or erase operation. However, since the memory cells are in a program or erase operation, they may be selected memory cells or unselected memory cells. In order to effectively perform a program or erase operation on a selected memory cell and to suppress unselected memory cells without disturbance, it is a difficult task to provide a suitable bias voltage for each memory cell under the limitation of process conditions. BRIEF SUMMARY OF THE PRESENT DISCLOSURE The present disclosure provides a three-dimensional memory device that can provide appropriate bit line voltages and source line voltages to individual memory cells. The three-dimensional memory device of the present disclosure includes a plurality of memory cell arrays, a plurality of bit line switches, and a plurality of source line switches. The memory cell array has a plurality of corresponding memory cell columns respectively coupled to a plurality of source lines and a plurality of bit lines. The bit line switches are respectively composed of a plurality of first transistors. The first ends of the first transistors are coupled to a common bit line, and the second ends of the first transistors are respectively coupled to the bit line. The source line switches are respectively composed of a plurality of second transistors. The second ends of the second transistors are coupled to the common source line, and the second ends of the second transistors are respectively coupled to the source line. The first transistor is a P-type transistor or an N-type transistor with a triple-well substrate, and the second transistor is a P-type transistor or an N-type transistor with a triple-well substrate. Based on the above, the three-dimensional memory device of the present disclosure constructs the source line switch and the bit line switch by a P-type transistor or an N-type transistor having a triple well region substrate. In the three-dimensional memory device of the present disclosure, the voltage on the well region of the P-type transistor and/or the N-type transistor can be controlled so that the source or the drain thereof can pass through a positive or a negative voltage. In this way, the source line switch and the bit line switch can provide appropriate voltages to the selected and unselected memory cells, so that each memory cell can complete the reading, programming and erasing operations. Drawings FIG. 1 is a schematic diagram of a three-dimensional memory device according to an embodiment of the disclosure. Fig. 2 is a schematic diagram of an implementation of an N-type transistor with a triple well substrate in a three-dimensional memory device according to an embodiment of the disclosure. Fig. 3A to 3D are schematic diagrams illustrating an access operation of the three-dimensional memory device according to the embodiments of the disclosure. Fig. 4A to 4D are schematic diagrams illustrating an access operation of a three-dimensional memory device according to another embodiment of the disclosure. Fig. 5A to 5D are schematic diagrams illustrating an access operation of a three-dimensional memory device according to another embodiment of the disclosure. Fig. 6A to 6D are schematic diagrams illustrating an access operation of a three-dimensional memory device according to another embodiment of the disclosure. Description of the reference numerals 100. 300, 400, 500, 600: Three-dimensional memory device 111. 112 Memory cell array 120. 130, 320, 330, 420, 430, 520, 530, 620, 630: A substrate 200N-type transistor 210N-type deep well region 220P-type well region 230N-type well region 231. 232N-type heavily doped region 233P-type heavily doped region 245 Insulating structure 250 Gate structure BLT 0-BLT 3 bit line switch CSL common source line CT (computed tomography) connecting structure GBL common bit line LBL 0-LBL 3 bit line LSL 0-LSL 3 source line M11-M24 transistor MC1, MC2 memory cell SLT 0-SLT 3 source line switch SMB selected memory cell block SMC selected memory cell WL0_0 to WL1_1, word lines Detailed Description Referring to fig. 1, fig. 1 is a schematic diagram of a three-dimensional memory device according to an embodiment of the disclosure. T