CN-115831749-B - Manufacturing method of high-reliability full-surrounding-gate MOSFET

Abstract

The invention relates to the technical field of integrated circuits, in particular to a manufacturing method of a high-reliability full-surrounding-gate MOSFET. The method comprises the following steps of S1 epitaxial growth, S2 ion implantation, S3 annealing, S4 etching, S5 film growth, S6 metal deposition, and forming a channel, wherein the step of growing an intrinsic silicon layer on a P+ substrate, the step of S2 ion implantation comprises the steps of carrying out ion implantation on the surface of the intrinsic silicon layer, the step of S4 etching comprises the step of carrying out etching on an ion implantation part on the P+ substrate, the step of carrying out film growth on an SiO 2 layer on the etched part, and the step of depositing metal on the thin SiO 2 layer. The structure can directly control the channel length of the device by changing the etching depth, and the manufacturing method has more concise process steps and improves the reliability of the device.

Inventors

• LIAO YONGBO
• WEI CHAO
• PENG PENG
• LIN JIACHENG
• XU FENGHE
• Yuan Pigen
• XU LU
• HUANG LETIAN

Assignees

• 电子科技大学长三角研究院(湖州)

Dates

Publication Date

20260508

Application Date

20221021

Claims (5)

1. 1. The manufacturing method of the high-reliability full-surrounding-gate MOSFET is characterized by comprising the following steps of: S1, epitaxial growth, namely growing an intrinsic silicon layer (2) on a P+ substrate (1); s2, ion implantation, namely implanting N+ ions on the surface of the intrinsic silicon layer (2) to form an N+ region (4) on the surface of the intrinsic silicon layer (2); S3 annealing to diffuse the N+ region (4), and further forming an N-region (5) in the centers of the P+ substrate (1) and the intrinsic layer N+ region (4), wherein the N+ region (4) and the N-region (5) are jointly called an active region (7); s4, etching the ion implantation part on the P+ substrate (1); S5, film growth, namely film growth of a SiO 2 layer (3) is carried out on the etched part; S6, depositing metal, namely depositing metal on the thin SiO 2 layer (3) to form a channel (8).
2. 2. The method of manufacturing a fully-enclosed gate MOSFET of claim 1, wherein the shape etched in step S4 is a semi-ellipsoidal region (6), square or rectangle, or other known shape.
3. 3. The method for manufacturing the full-surrounding gate MOSFET with high reliability according to claim 2, wherein the bottom end of the semi-ellipsoidal region (6) is required to be etched into the P+ substrate (1).
4. 4. The method of manufacturing a high reliability fully-surrounding gate MOSFET of claim 1 wherein the deposited metal is used as the gate electrode.
5. 5. The method of manufacturing a highly reliable fully-surrounding gate MOSFET of claim 1, wherein the length of the channel (8) in the step S6 is 1nm to 100nm.

Description

Manufacturing method of high-reliability full-surrounding-gate MOSFET Technical Field The invention relates to the technical field of integrated circuits, in particular to a manufacturing method of a high-reliability full-surrounding-gate MOSFET. Background The concept of semiconductors as plate capacitors has long been developed as MOSFETs (metal-oxide-semiconductor field effect transistors). MOSFETs are core devices and mainstream devices in today's leading-edge very large scale integrated circuits, such as microprocessors, semiconductor memories, etc., and are also an important power device. Currently, in order to meet the requirements of low power consumption, high speed and high density of chips, the IC industry is continuously improving the basic device structure of the IC, and the process steps of the device are also simplified as much as possible. The traditional PMOS is used as an example, and the process steps mainly comprise 5 steps, namely (1) one-time oxidation, (2) boron diffusion to manufacture a drain-source region, (3) a gate oxidation process, (4) a phosphorus treatment process and (5) a nitrogen blowing (nitrogen baking) process. It can be seen that the conventional MOSFET is relatively complex in its fabrication process and is easily contaminated by metal ions, mainly na+, during the multiple diffusion process, and the channel length of the conventional MOSFET is limited to the photolithography machine, and the accuracy is difficult to control. Disclosure of Invention First, problems to be solved The manufacturing method is mainly used for solving the problems that the manufacturing process of the traditional MOSFET is complex, the channel length is limited by a photoetching machine and the like, and the manufacturing method of the high-reliability full-surrounding gate MOSFET is provided. (II) technical scheme The invention relates to a manufacturing method of a high-reliability full-surrounding gate MOSFET, which comprises the following steps: s1, epitaxial growth, namely growing an intrinsic silicon layer on a P+ substrate; S2, ion implantation, namely performing ion implantation on the surface of the intrinsic silicon layer; S3, annealing; S4, etching the ion implantation part on the P+ substrate; s5, film growth, namely film growth of a SiO 2 layer is carried out on the etched part; And S6, depositing metal, namely depositing metal on the thin SiO 2 layer to form a channel. As a preferable technical scheme, the injection of N+ ions is mainly performed in the step S2, and an N+ region can be formed on the surface of the intrinsic silicon layer. As a preferred technical solution, an annealing process is used in step S3, so that diffusion occurs in the n+ region. As a preferred technical scheme, an annealing process is used in the step S3, and an N-region is further formed in the center of the p+ substrate and the n+ region of the intrinsic layer. As a preferred embodiment, the n+ region and the N-region are collectively referred to as an active region. As a preferable technical scheme, the shape etched in the step S4 is a semi-ellipsoidal area or square or rectangle, or other known shape. As a preferred technical solution, the bottom end of the etched region needs to be etched into the p+ substrate. As a preferred embodiment, a deposited metal is used as the gate electrode. As a preferred technical scheme, the channel length in the step S6 is 1nm to 100nm. (III) beneficial effects The invention has the beneficial effects that: 1. the structure of the high-reliability full-surrounding grid MOSFET is researched, compared with the traditional MOSFET technology, the manufacturing method is simpler in process steps, the diffusion times are reduced, the possibility of Na+ contamination is effectively reduced, and the reliability of the device is improved. 2. The full-surrounding gate MOSFET manufactured by the method can directly control the channel length of the device by changing the etching depth, so that the difficulty in adjusting the channel length is greatly reduced. Drawings In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. FIG. 1 is a schematic flow chart of the present invention; FIG. 2 is a graph of a static characteristic simulated transfer characteristic of the present invention; FIG. 3 is a graph of a static characteristic simulated output characteristic of the present invention; 1-P+ substrate, 2-intrinsic silicon layer, 3-SiO 2 layer, 4-N+ region, 5-N region, 6-semi-ellipsoidal region, 7-active region, and 8-channel. Detailed Description The structure of the high-reliabil