CN-115831873-B - Semiconductor device and method for manufacturing the same

Abstract

Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a gate structure, an n-type source/drain feature, a p-type source/drain feature, an NFET channel, and a PFET channel. The gate structure is over the substrate. The n-type source/drain features are located at opposite first and second sides of the gate structure, respectively. The p-type source/drain features are located at opposite third and fourth sides of the gate structure, respectively. An NFET channel extends within the gate structure and connects the n-type source/drain components. The PFET channel extends within the gate structure and connects the p-type source/drain components. The NFET channel and PFET channel are vertically spaced apart by a gate structure.

Inventors

• LIN SHIYA
• DU JIANDE
• Cai Zhongen
• LIU ZHIWEI

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260512

Application Date

20220610

Priority Date

20220222

Claims (20)

1. 1. A method of manufacturing a semiconductor device, comprising: forming a first semiconductor layer on a substrate and forming a second semiconductor layer over the first semiconductor layer, the first and second semiconductor layers having first sidewalls extending along a first direction and second sidewalls extending along a second direction different from the first direction; Forming a first internal spacer on the first sidewall of the first semiconductor layer; forming a p-type source/drain structure on the first sidewall of the second semiconductor layer; forming a second internal spacer on the second sidewall of the second semiconductor layer; Forming an n-type source/drain structure on the second sidewall of the first semiconductor layer, and A gate structure is formed at least partially between the first semiconductor layer and the second semiconductor layer.
2. 2. The method of claim 1, wherein the second semiconductor layer is formed of a different material than the first semiconductor layer.
3. 3. The method of claim 1, wherein the first semiconductor layer has a tensile strain.
4. 4. The method of claim 1, wherein the second semiconductor layer has a compressive strain.
5. 5. The method of claim 1, further comprising: The first sidewall of the first semiconductor layer is etched such that the first sidewall of the first semiconductor layer is laterally recessed from the first sidewall of the second semiconductor layer prior to forming the first inner spacer.
6. 6. The method of claim 1, further comprising: The second sidewall of the second semiconductor layer is etched such that the second sidewall of the second semiconductor layer is laterally recessed from the second sidewall of the first semiconductor layer prior to forming the second internal spacer.
7. 7. The method of claim 1, further comprising: After forming the first internal spacers, a bottom dielectric isolation structure is formed on the substrate, wherein the p-type source/drain structures are respectively formed on the bottom dielectric isolation structure.
8. 8. The method of claim 1, further comprising: After forming the second internal spacers, a bottom dielectric isolation structure is formed on the substrate, wherein the n-type source/drain structures are respectively formed on the bottom dielectric isolation structure.
9. 9. The method of claim 1, further comprising: forming a third semiconductor layer over the first semiconductor layer before forming the second semiconductor layer, and After forming the p-type source/drain structure and the n-type source/drain structure, removing the third semiconductor layer to form an opening between the first semiconductor layer and the second semiconductor layer, Wherein the gate structure is at least partially formed in the opening between the first semiconductor layer and the second semiconductor layer.
10. 10. The method of claim 1, further comprising: A common source/drain contact is formed that electrically connects one of the p-type source/drain structures with one of the n-type source/drain structures.
11. 11. The method of claim 10, wherein the common source/drain contact has an L-shaped top-down profile.
12. 12. A method of manufacturing a semiconductor device, comprising: Forming a layer stack on a substrate, the layer stack including an NFET channel layer, a PFET channel layer, and a sacrificial layer between the NFET channel layer and the PFET channel layer; Performing a first selective etch process on an opposite first sidewall of the layer stack, wherein the first selective etch process etches the NFET channel layer at a faster etch rate than the PFET channel layer; forming a p-type epitaxial structure on the first sidewall of the layer stack after performing the first selective etching process; performing a second selective etch process on an opposite second sidewall of the layer stack, wherein the second selective etch process etches the PFET channel layer at a faster etch rate than the NFET channel layer; forming an n-type epitaxial structure on the second sidewall of the layer stack after performing the second selective etching process, and The sacrificial layer is replaced with a gate structure.
13. 13. The method of claim 12, further comprising: An internal spacer is formed on the first sidewall of the layer stack after performing the first selective etch process and before forming the p-type epitaxial structure, wherein the internal spacer is positioned on the NFET channel layer.
14. 14. The method of claim 12, further comprising: an internal spacer is formed on the second sidewall of the layer stack after performing the second selective etch process and before forming the n-type epitaxial structure, wherein the internal spacer is positioned on the PFET channel layer.
15. 15. The method of claim 12, wherein replacing the sacrificial layer with the gate structure comprises: performing a third selective etching process to remove the sacrificial layer, leaving an opening between the PFET channel layer and the NFET channel layer, and The gate structure is formed at least partially in the opening between the PFET channel layer and the NFET channel layer.
16. 16. A semiconductor device, comprising: A gate structure over the substrate; An n-type source/drain feature and a p-type source/drain feature disposed about the gate structure, wherein the gate structure has a quadrilateral profile when viewed from a top view, the n-type source/drain feature being located at opposing first and second sides of the quadrilateral profile of the gate structure, respectively, and the p-type source/drain feature being located at opposing third and fourth sides of the quadrilateral profile of the gate structure, respectively; An NFET channel extending within the gate structure and connecting the n-type source/drain features, and PFET channels extending within the gate structure and connecting the p-type source/drain features, the NFET channels and the PFET channels being vertically spaced apart from the gate structure as viewed in cross-section.
17. 17. The semiconductor device of claim 16, further comprising: a first internal spacer separating the NFET channel from a first one of the p-type source/drain features, and A second internal spacer separates the NFET channel from a second one of the p-type source/drain features.
18. 18. The semiconductor device of claim 17, further comprising: a third internal spacer separating the PFET channel from a first one of the n-type source/drain features, and A fourth inner spacer separating the PFET channel from a second one of the n-type source/drain features, wherein the first inner spacer and the second inner spacer are spaced apart along a first direction and the third inner spacer and the fourth inner spacer are spaced apart along a second direction different from the first direction.
19. 19. The semiconductor device of claim 16, further comprising: a common source/drain contact electrically connecting one of the p-type source/drain features and one of the n-type source/drain features, the common source/drain contact having an L-shaped top-down profile.
20. 20. The semiconductor device of claim 16, further comprising: Vdd contact over one of the p-type source/drain features, and A Vss contact is located over one of the n-type source/drain features, wherein the Vdd contact and the Vss contact extend in different directions from a top view.

Description

Semiconductor device and method for manufacturing the same Technical Field Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same. Background Semiconductor devices are used in a variety of electronic applications, such as, for example, computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon. Transistors are elements widely used in semiconductor devices. For example, there may be thousands of transistors on a single Integrated Circuit (IC) in some applications. One common type of transistor used in semiconductor device fabrication is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The two transistors may be coupled together to form an inverter. Disclosure of Invention According to one aspect of an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device including forming a first semiconductor layer over a substrate and forming a second semiconductor layer over the first semiconductor layer, the first semiconductor layer and the second semiconductor layer having a first sidewall extending along a first direction and a second sidewall extending along a second direction different from the first direction, forming a first internal spacer on the first sidewall of the first semiconductor layer, forming a p-type source/drain structure on the first sidewall of the second semiconductor layer, forming a second internal spacer on the second sidewall of the second semiconductor layer, forming an n-type source/drain structure on the second sidewall of the first semiconductor layer, and forming a gate structure at least partially between the first semiconductor layer and the second semiconductor layer. According to another aspect of an embodiment of the present invention, a method of fabricating a semiconductor device is provided that includes forming a layer stack on a substrate, the layer stack including an n-type field effect transistor (NFET) channel layer, a p-type field effect transistor (PFET) channel layer, and a sacrificial layer between the NFET channel layer and the PFET channel layer, performing a first selective etch process on opposing first sidewalls of the layer stack, wherein the first selective etch process etches the NFET channel layer at a faster etch rate than the PFET channel layer, forming a p-type epitaxial structure on the first sidewalls of the layer stack after the first selective etch process is performed, performing a second selective etch process on opposing second sidewalls of the layer stack, wherein the second selective etch process etches the PFET channel layer at a faster etch rate than the NFET channel layer, forming an n-type epitaxial structure on the second sidewalls of the layer stack after the second selective etch process is performed, and replacing the sacrificial layer with a gate structure. According to yet another aspect of an embodiment of the present invention, there is provided a semiconductor device including a gate structure over a substrate, n-type and p-type source/drain features disposed about the gate structure, wherein the gate structure has a quadrilateral profile in plan view, the n-type source/drain features being located at opposite first and second sides of the quadrilateral profile of the gate structure, respectively, and the p-type source/drain features being located at opposite third and fourth sides of the quadrilateral profile of the gate structure, respectively, an NFET channel extending within the gate structure and connecting the n-type source/drain features, and a PFET channel extending within the gate structure and connecting the p-type source/drain features, the NFET channel and the PFET channel being vertically spaced apart by the gate structure in cross-section view. Drawings The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1 is a schematic circuit diagram of an example CMOS inverter according to some embodiments of the present disclosure. Fig. 2A-19C are top, perspective, and cross-sectional views at an intermediate stage of inverter fabrication, according to some embodiments of the present disclosure. Fig. 20A and 20B are cross-sectional views of an inverter according to some embodiments of the present disclosure, wherein fig. 2